Analog neural memory array storing synapsis weights in differential cell pairs in artificial neural network
Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.
1. A system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns; and
a dummy column next to at least one of the physically adjacent pairs of columns;
wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−).
2. The system of claim 1 , wherein the dummy column serves as a source line pull down bit line.
3. The system of claim 1 , wherein the non-volatile memory cells in the array are split gate flash memory cells.
4. The system of claim 1 , wherein the non-volatile memory cells in the array are stacked gate flash memory cells.
5. The system of claim 1 , further comprising a summer for summing outputs from one or more bit lines.
6. The system of claim 5 , wherein the summer is adjustable based on a variable resistor.
7. The system of claim 5 , wherein the summer is adjustable based on a variable capacitor.
8. The system of claim 5 , wherein the summer comprises a switched capacitor circuit and an operational amplifier.
9. The system of claim 5 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.
10. The system of claim 9 , wherein the analog-to-digital converter comprises a successive approximation register.
11. The system of claim 10 , wherein the analog-to-digital converter is a pipelined analog-to-digital converter.
12. A system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns;
wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−); and
wherein the array comprises a set of columns of non-volatile memory cells utilized as a redundant array.
13. The system of claim 12 , wherein the dummy column serves as a source line pull down bit line.
14. The system of claim 12 , wherein the non-volatile memory cells in the array are split gate flash memory cells.
15. The system of claim 12 , wherein the non-volatile memory cells in the array are stacked gate flash memory cells.
16. The system of claim 12 , further comprising a summer for summing outputs from one or more bit lines.
17. The system of claim 16 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.
18. A system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns; and
a redundant column, wherein values stored in a W+ column or a W− column are remapped to the redundant column;
wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(w+)−(W−).
19. The system of claim 18 , wherein the remapping removes coupling between two adjacent cells in an adjacent pair of columns.
20. The system of claim 18 , wherein the remapping re-distributes one or more of power or voltage drop between bit lines.
21. The system of claim 18 , wherein the remapping remaps the noise cells into the redundant column.
22. The system of claim 18 , wherein the dummy column serves as a source line pull down bit line.
23. The system of claim 18 , wherein the non-volatile memory cells in the array are split gate flash memory cells.
24. The system of claim 18 , wherein the non-volatile memory cells in the array are stacked gate flash memory cells.
25. The system of claim 18 , further comprising a summer for summing outputs from one or more bit lines.
26. The system of claim 25 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.