Patent Assignment
Reel/Frame 059264/0384
Release of Security Interest
Recorded: 2022-02-28
Received: 2022-02-28
Pages: 34
Assignor
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Executed: 2022-02-18
Assignees
MICROCHIP TECHNOLOGY INCORPORATED
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
SILICON STORAGE TECHNOLOGY, INC.
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
ATMEL CORPORATION
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
MICROSEMI CORPORATION
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
MICROSEMI STORAGE SOLUTIONS, INC.
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
Covered Properties
(100)
Lead Frames for Semiconductor Packages with Increased Reliability and Related Semiconductor Device Packages and Methods
Application:
17/314,535 →
Metal-Insulator-Metal (Mim) Capacitor and Thin-Film Resistor (Tfr) Formed in an Integrated Circuit Structure
Application:
17/308,270 →
Metal-Oxide-Metal (Mom) Capacitors for Integrated Circuit Monitoring
Application:
17/306,019 →
Systems and Methods to Remove Input Voltage Dependency in a Power Converter
Application:
17/244,882 →
System and Method for Synchronizing Nodes in a Network Device
Application:
17/242,493 →
Flash Memory Cell and Associated High Voltage Row Decoder
Application:
17/239,397 →
Method and Apparatus for Reading a Flash Memory Device
Application:
17/234,993 →
Integrated Circuit E-Fuse Having an E-Fuse Element Providing a Diffusion Barrier for Underlying E-Fuse Terminals
Application:
17/233,311 →
Electronic Fuse (E-Fuse) with Displacement-Plated E-Fuse Terminals
Application:
17/233,367 →
Thin-Film Resistor (Tfr) Having a Tfr Element Providing a Diffusion Barrier for Underlying Tfr Heads
Application:
17/233,285 →
Semiconductor Device Packages Including Multiple Lead Frames and Related Methods
Application:
17/301,864 →
Thin-Film Resistor (Tfr) with Displacement-Plated Tfr Heads
Application:
17/233,342 →
Automatic Threshold Adjustment for USB Power Delivery to Work with Cables Out of Specification
Application:
17/229,083 →
Amplified Charge Cancellation in a Touch Sensor, and Related Systems, Methods, and Devices
Application:
17/301,744 →
Provisioning Headless Wifi Devices and Related Systems, Methods and Devices
Application:
17/301,522 →
Tswitch with Reduced Current Leakage
Application:
63/169,571 →
Digital Output Mechanisms for Analog Neural Memory in a Deep Learning Artificial Neural Network
Application:
17/219,352 →
Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device
Application:
17/213,675 →
Circuitry for Autonomously Measuring Analog Signals and Related Systems, Methods, and Devices
Application:
17/301,105 →
Multi-Bias Mode Current Conveyor, Configuring a Multi-Bias Mode Current Conveyor, Touch Sensing Systems Including a Multi-Bias Mode Current Conveyor, and Related Systems, Methods and Devices
Application:
17/301,080 →
Low Connection Count Interface Wake Source Communication According to 10SPE Local and Remote Wake and Related Systems, Methods, and Devices
Application:
17/301,094 →
Recognizing an Object Using Capacitive Sensing
Application:
17/249,925 →
DC-DC Converter With Improved Line Transient Rejection
Application:
17/198,911 →
Methods and Systems for Determining a Noise-Robust Acquisition Configuration for Operating a Sensor System
Application:
17/198,860 →
Architectures for Storing and Retrieving System Data in a Non-Volatile Memory System
Application:
17/199,383 →
Set-While-Verify Circuit And Reset-While Verify Circuit For Resistive Random Access Memory Cells
Application:
17/199,243 →
Low-Latency Macsec Authentication
Application:
17/193,172 →
Programming Analog Neural Memory Cells in Deep Learning Artificial Neural Network
Application:
17/191,392 →
Concurrent Write and Verify Operations in an Analog Neural Memory
Application:
17/190,376 →
Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate With Silicide On Conductive Blocks
Application:
17/185,709 →
Precise Data Tuning Method and Apparatus for Analog Neural Memory in an Artificial Neural Network
Application:
17/185,725 →
Output Circuits for an Analog Neural Memory System for Deep Learning Neural Network
Application:
17/181,656 →
Method Of Forming Split Gate Memory Cells With Thinner Tunnel Oxide
Application:
17/179,057 →
Virtual Ground Non-Volatile Memory Array
Application:
17/178,520 →
Base Assemblies Having Conductive Pads for Knob on Display Devices and Related Systems, Methods, and Devices
Application:
17/174,963 →
Burn-In Board Including Strip Socket with Integrated Heating for High Volume Burn-in of Semiconductor Devices
Application:
17/174,392 →
Thin-Film Resistor (Tfr) with Improved Contacts
Application:
17/170,975 →
Interfacing a Number of Serial Communication Interfaces with a Parallel Communication Interface, and Related Systems, Methods, and Apparatuses
Application:
17/171,697 →
Method, System and Apparatus for Suppressing Controller Area Network Bus Ringing
Application:
17/164,934 →
Split-Gate Non-Volatile Memory Cells with Erase Gates Disposed Over Word Line Gates, and Method of Making Same
Application:
17/165,934 →
Integrated Circuit Bond Pad with Multi-Material Toothed Structure
Application:
17/163,645 →
Heads-Up Display Using Electrochromic Elements
Application:
17/160,958 →
Three-Dimensional Metal-Insulator-Metal (Mim) Capacitor
Application:
17/155,431 →
Method of Forming a Device with Planar Split Gate Non-Volatile Memory Cells, High Voltage Devices and Finfet Logic Devices
Application:
17/151,944 →
Split Gate Non-Volatile Memory Cells, Hv and Logic Devices with Finfet Structures, and Method of Making Same
Application:
17/152,441 →
Split-Gate, 2-Bit Non-Volatile Memory Cell with Erase Gate Disposed Over Word Line Gate, and Method of Making Same
Application:
17/152,696 →
System and Method for Scheduling Sharable Pcie Endpoint Devices
Application:
17/151,316 →
Partitionable Neural Network for Solid State Drives
Application:
17/148,200 →
Systems and Methods for Detecting Forcer Misalignment in a Wafer Prober
Application:
17/147,778 →
Redundant Angular Position Sensor and Associated Method of Use
Application:
17/146,875 →
Method, System and Apparatus for Constant, High Switching Frequency and Narrow Duty Ratio Pwm Control of Dc-Dc Converters and Accurate Pfm Control at Light Load
Application:
17/145,944 →
Adaptive Bias Decoder to Provide a Voltage to a Control Gate Line in an Analog Neural Memory Array in Artificial Neural Network
Application:
17/140,924 →
METHOD FOR ERASING A ReRAM MEMORY CELL
Application:
17/140,064 →
Sensors, Autonomous Sensors and Related Systems, Methods and Devices
Application:
17/247,954 →
Electrical Energy Loss Detection
Application:
17/247,837 →
Transparently Attached Flash Memory Security
Application:
17/133,115 →
Input and Digital Output Mechanisms for Analog Neural Memory in a Deep Learning Artificial Neural Network
Application:
17/133,395 →
Method for forming hermetic package for a power semiconductor
Application:
17/129,144 →
Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate
Application:
17/129,865 →
Verifying or Reading a Cell in an Analog Neural Memory in a Deep Learning Artificial Neural Network
Application:
17/125,459 →
Input and Digital Output Mechanisms for Analog Neural Memory in a Deep Learning Artificial Neural Network
Application:
17/121,555 →
Integrated Inductor with a Stacked Metal Wire
Application:
17/117,288 →
Backside Interconnect for Integrated Circuit Package Interposer
Application:
17/111,973 →
Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification
Application:
17/111,218 →
Method and System for Enhanced Spi Communication
Application:
17/109,315 →
Front-End Circuitry for a Data Receiver and Related Systems, Methods, and Devices
Application:
17/247,148 →
Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory in Deep Learning Artificial Neural Network
Application:
17/104,385 →
Method and Apparatus for Phase Current Balancing in a Multi-Phase Dc-to-Dc Converter
Application:
17/101,498 →
Self-Timed Sensing Architecture for a Non-Volatile Memory System
Application:
17/095,331 →
Temperature Compensation in an Analog Memory Array by Changing a Threshold Voltage of a Selected Memory Cell in the Array
Application:
17/095,661 →
Analog Neural Memory Array in Artificial Neural Network with Source Line Pulldown Mechanism
Application:
17/090,481 →
Regression Neural Network for Identifying Threshold Voltages to be Used in Reads of Flash Memory Devices
Application:
17/089,891 →
Obfuscating Cryptographic Parameters Used in Elliptical Curve Cryptography, and Related Systems and Devices
Application:
17/086,007 →
Analog Neural Memory Array in Artificial Neural Network Comprising Logical Cells and Improved Programming Mechanism
Application:
17/082,956 →
Integrated Circuit (Ic) Package with Integrated Inductor Having Core Magnetic Field (B Field) Extending Parallel to Substrate
Application:
17/074,848 →
Ovens for Atomic Clocks and Related Methods
Application:
16/949,222 →
Charge Pump for Use in Non-Volatile Flash Memory Devices
Application:
17/075,691 →
System and Method for Auto-Recovery in Lockstep Processors
Application:
17/075,493 →
System and Method for Monitoring Analog Front-End (Afe) Circuitry of an Inductive Position Sensor
Application:
17/075,157 →
Touch Sensor Signal Integration
Application:
16/949,218 →
Non-Volatile Memory System Using Strap Cells in Source Line Pull Down Circuits
Application:
17/074,103 →
Thin Film Resistor (Tfr) Formed in an Integrated Circuit Device Using an Oxide Cap Layer as a Tfr Etch Hardmask
Application:
17/071,584 →
Thin Film Resistor (Tfr) Formed in an Integrated Circuit Device Using Wet Etching of a Dielectric Cap
Application:
17/071,356 →
Thin Film Resistor (Tfr) Formed in an Integrated Circuit Device Using Tfr Cap Layer(S) as an Etch Stop and/or Hardmask
Application:
17/071,442 →
Microcontroller with Increasing Protected Storage Area and Erase Protection
Application:
63/091,333 →
Finfet Split Gate Non-Volatile Memory Cells with Enhanced Floating Gate to Floating Gate Capacitive Coupling
Application:
17/069,563 →
Foreign Object Detection in Wireless Charging Systems and Related Systems, Methods, and Devices
Application:
16/949,003 →
Near Constant Delay Comparator for Closed-Loop System
Application:
17/065,920 →
Synchronization of Sequence Numbers in a Network
Application:
16/948,908 →
Motor-Current Control Process for Permanent-Magnet Synchronous Motors and Related Systems, Methods and Devices
Application:
16/948,906 →
Low Cost Power Line Modem
Application:
17/037,919 →
EtherCAT Controllers
Application:
17/030,439 →
Low Cost Cryptographic Accelerator
Application:
16/948,480 →
Precision Tuning of a Page or Word of Non-Volatile Memory Cells and Associated High Voltage Circuits for an Analog Neural Memory Array in an Artificial Neural Network
Application:
17/024,410 →
System and Method for Data Sampler Drift Compensation
Application:
17/022,480 →
Method of Forming a Three-Gate Non-Volatile Flash Memory Cell Using Two Polysilicon Deposition Steps
Application:
17/021,678 →
Systems and Methods for Improved Root Mean Square (Rms) Measurement
Application:
17/019,514 →
Integrated Circuit (IC) Device Including A Force Mitigation System For Reducing Under-Pad Damage Caused By Wire Bond
Application:
17/019,768 →
Techniques for Routing Signals Using Inactive Sensor Regions of Touch Sensors and Related Systems and Devices
Application:
16/948,270 →
Pulse-Width Modulation and Arbitration for Contextual and Uniform Led Illumination in Usb Applications
Application:
17/013,978 →