BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER
Methods are provided for forming an integrated circuit (IC) package interposer configured for back-side attachment. A porous silicon double layer is formed on a bulk silicon wafer, e.g., using a controlled anodization, the porous silicon double layer including two porous silicon layers having different porosities. An interposer is formed over the porous silicon double layer, the interposer including back-side contacts, front-side contacts, and conductive structures (e.g., vias and metal interconnect) extending through the interposer to connect selected back-side contacts with selected front-side contacts. The structure is then split at the interface between the first and second porous silicon layers of the silicon double layer, and the interposer including the second porous silicon layers is inverted and etched to remove the second silicon layer and expose the back-side contacts, such that the exposed back-side contacts can be used for back-side attachment of the interposer to a package substrate or other structure.
1 . A method of forming an integrated circuit (IC) package interposer configured for back-side attachment, comprising:
forming a base silicon wafer including a porous silicon double layer over a bulk silicon region, the porous silicon double layer including a first porous silicon layer having a first porosity adjacent a second porous silicon layer having a second porosity different than the first porosity;
forming an interposer over the porous silicon double layer, the interposer including:
back-side contacts on a back side of the interposer;
front-side contacts on a front side of the interposer; and
conductive structures extending through a vertical thickness of the interposer to connect selected back-side contacts with selected front-side contacts;
splitting the porous silicon double layer to separate the first porous silicon layer from the second porous silicon layer, and removing the separated first porous silicon layer and bulk silicon region; and
after splitting the porous silicon double layer, removing at least the second silicon layer to expose the back-side contacts, the exposed back-side contacts configured for attachment to a package substrate or other structure.
2 . The method of claim 1 , further comprising using the exposed back-side contacts to back-side mount the IC package interposer to the package substrate or other structure.
3 . The method of claim 2 , comprising soldering the exposed back-side contacts to the package substrate or other structure.
4 . The method of claim 2 , comprising direct attaching the exposed back-side contacts to the package substrate or other structure.
5 . The method of claim 1 , further comprising mounting at least one die to at least one front-side contact.
6 . The method of claim 5 , further comprising mounting the at least one die to the at least one front-side contact and encapsulating the at least one mounted die prior to splitting the porous silicon double layer.
7 . The method of claim 5 , further comprising mounting at least one die to at least one front-side VMD contact in a vertical orientation and mounting at least one die to at least one front-side HMD contact in a horizontal orientation.
8 . The method of claim 1 , wherein splitting the porous silicon double layer to separate the first porous silicon layer from the second porous silicon layer comprises using a water jet to separate the first porous silicon layer from the second porous silicon layer.
9 . The method of claim 1 , wherein forming the interposer comprises forming a plurality of vias and at least one metal layer between the back-side contacts and front-side contacts to define the conductive structures extending through the vertical thickness the interposer to connect selected back-side contacts with selected front-side contacts.
10 . A method of forming an integrated circuit (IC) package interposer configured for back-side attachment, comprising:
performing an anodizing process on a base silicon wafer to form a multi-layer silicon region including a first porous silicon layer having a first porosity adjacent a second porous silicon layer having a second porosity different than the first porosity;
forming an interposer over the multi-layer silicon region, the interposer including:
back-side contacts on a back side of the interposer;
front-side contacts on a front side of the interposer; and
conductive structures extending through a vertical thickness of the interposer to connect selected back-side contacts with selected front-side contacts;
mounting at least one die to at least one of the front-side contacts;
splitting the multi-layer silicon region to separate the first porous silicon layer from the second porous silicon layer; and
after splitting the multi-layer silicon region, removing at least the second silicon layer to expose the back-side contacts, the exposed back-side contacts configured for attachment to a package substrate or other structure.
11 . The method of claim 10 , further comprising using the exposed back-side contacts to back-side mount the IC package interposer to the package substrate or other structure.
12 . The method of claim 11 , comprising soldering the exposed back-side contacts to the package substrate or other structure.
13 . The method of claim 11 , comprising direct attaching the exposed back-side contacts to the package substrate or other structure.
14 . The method of claim 10 , further comprising encapsulating the at least one mounted die prior to splitting the porous silicon double layer.
15 . The method of claim 10 , wherein mounting at least one die to at least one of the front-side contacts comprises mounting at least one die to at least one front-side VMD contact in a vertical orientation and mounting at least one die to at least one front-side HMD contact in a horizontal orientation.
16 . The method of claim 10 , wherein splitting the multi-layer silicon region to separate the first porous silicon layer from the second porous silicon layer comprises using a water jet to separate the first porous silicon layer from the second porous silicon layer.
17 . The method of claim 10 , wherein forming the interposer comprises forming a plurality of vias and at least one metal layer between the back-side contacts and front-side contacts to define the conductive structures extending through the vertical thickness of the interposer to connect selected back-side contacts with selected front-side contacts.
18 . An integrated circuit (IC) package, comprising:
an IC package substrate; and
an interposer, comprising:
back-side contact pads on a back side of the interposer;
front-side contact pads on a front side of the interposer; and
conductive structures extending through a vertical thickness of the interposer to connect selected back-side contact pads with selected front-side contact pads;
at least one die mounted to the front-side contact pads;
wherein the interposer is back-side attached to an IC package substrate by the back-side contact pads.
19 . The IC package of claim 18 , wherein the interposer includes no wafer substrate.
20 . The IC package of claim 18 , wherein the interposer includes no through-silicon vias (TSVs).