IP Library Granted Patent US 11,500,789
Granted Patent B2
US 11,500,789 · App. 17/229,083 · Granted Nov 15, 2022

Automatic threshold adjustment for USB power delivery to work with cables out of specification

Inventors: Atish Ghosh (Austin, TX); Hari Kishore Rajendran (Tamil Nadu, IN); Sandhya Asokan (Tamilnadu, IN)
Assignee: Microchip Technology Incorporated
G06F13/102G06F13/4282G06F2213/0042
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Quick Facts
Patent No.
US 11,500,789
App. No.
17/229,083
Filed
Apr 13, 2021
Granted
Nov 15, 2022
Kind
B2
Examiner
YU, HENRY W
Art Unit
2181
USPC
710/36
Abstract

An apparatus includes a bi-phase mark coded (BMC) input port configured to receive BMC signals from a universal serial bus (USB) cable. The apparatus further includes a threshold adjustment circuit configured to generate a threshold, and a comparator configured to compare an input BMC signal from the BMC input port and the threshold and based on the comparison, generate an adjusted input BMC signal. The threshold adjustment circuit is further configured to adjust the threshold based upon the input BMC signal.

Claims (48)

1. An apparatus, comprising:

a bi-phase mark coded (BMC) input port to receive BMC signals from a universal serial bus (USB) cable;

a threshold adjustment circuit to generate a voltage threshold;

and

a comparator to:

compare an input BMC signal from the BMC input port and the voltage threshold; and

based on the comparison, generate an adjusted input BMC signal;

wherein the threshold adjustment circuit is to

adjust the voltage threshold based upon the input BMC signal through evaluation of the adjusted input BMC signal;

determine whether the adjusted input BMC signal is idle; and

based on a determination that the adjusted input BMC is idle, adjust the voltage threshold to an estimated voltage threshold value.

2. The apparatus of claim 1 , wherein the threshold adjustment circuit is to adjust the voltage threshold based upon relative durations of logic high signals and logic low signals over a defined time length of the input BMC signal.

3. The apparatus of claim 2 , wherein the threshold adjustment circuit is to raise or lower the voltage threshold until the durations of logic high signals and logic low signals over a defined time length of the input BMC signal are approximately equal.

4. The apparatus of claim 3 , wherein the defined time length is four bits of the input BMC signal.

5. The apparatus of claim 1 , wherein threshold adjustment circuit is to determine the estimated voltage threshold value by incrementally adjusting the voltage threshold until the adjusted input BMC is no longer idle.

6. The apparatus of claim 1 , wherein threshold adjustment circuit is to:

determine a current passing through the USB cable;

determine an impedance of the USB cable; and

determine the estimated voltage threshold value by a calculation of a voltage resulting from the current and the impedance.

7. A method, comprising:

receiving bi-phase mark coded (BMC) signals at a BMC input port from a universal serial bus (USB) cable;

generating a voltage threshold;

comparing an input BMC signal from BMC input port and the voltage threshold;

based on the comparison, generating an adjusted input BMC signal;

adjusting the voltage threshold based upon the input BMC signal;

determining whether the adjusted input BMC signal is idle; and

based on a determination that the adjusted input BMC is idle, adjusting the voltage threshold to an estimated voltage threshold value;

wherein adjusting the voltage threshold based on the input BMC signal includes evaluating the adjusted input BMC signal.

8. The method of claim 7 , wherein the voltage threshold is adjusted based upon relative durations of logic high signals and logic low signals over a defined time length of the input BMC signal.

9. The method of claim 8 , wherein the voltage threshold is adjusted by raising or lowering the voltage threshold until the durations of logic high signals and logic low signals over a defined time length of the input BMC signal are approximately equal.

10. The method of claim 9 , wherein the defined time length is four bits of the input BMC signal.

11. The method of claim 7 , comprising determining the estimated voltage threshold value by incrementally adjusting the voltage threshold until the adjusted input BMC is no longer idle.

12. The method of claim 7 , comprising:

determining a current passing through the USB cable;

determining an impedance of the USB cable; and

determining the estimated voltage threshold value by calculated the voltage resulting from the current and the impedance.

13. A universal serial bus (USB) element, comprising:

a bi-phase mark coded (BMC) input port to receive BMC signals from a USB cable;

a threshold adjustment circuit to generate a voltage threshold; and

a comparator to:

compare an input BMC signal from the BMC input port and the voltage threshold; and

based on the comparison, generate an adjusted input BMC signal;

wherein the threshold adjustment circuit is to;

adjust the voltage threshold based upon the input BMC signal through evaluation of the adjusted input BMC signal;

determine whether the adjusted input BMC signal is idle; and

based on a determination that the adjusted input BMC is idle, adjust the voltage threshold to an estimated voltage threshold value.

14. The USB element of claim 13 , wherein the threshold adjustment circuit is to adjust the voltage threshold based upon relative durations of logic high signals and logic low signals over a defined time length of the input BMC signal.

15. The USB element of claim 14 , wherein the threshold adjustment circuit is to raise or lower the voltage threshold until the durations of logic high signals and logic low signals over a defined time length of the input BMC signal are approximately equal.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059358/0398 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058213/0959 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2021
From: GHOSH, ATISH; RAJENDRAN, HARI KISHORE; ASOKAN, SANDHYA
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 055911/0133 →