Machine learning based methods and apparatus for integrated circuit design delay calculation and verification
A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.
1. A method for integrated circuit design with delay verification comprising:
storing configuration files of a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model;
receiving a user design;
extracting feature values from the user design for each slew-rate feature, net-delay feature and cell-delay feature to obtain slew-rate feature values, net-delay feature values and cell-delay feature values;
loading the slew-rate ML model configuration files to form a slew-rate inference core;
performing operations of the slew-rate inference core using the extracted slew-rate feature values as input to calculate predicted slew-rate values;
loading the net-delay ML model configuration files to form a net-delay inference core;
performing operations of the net-delay inference core using the extracted net-delay feature values as input to calculate predicted net-delay values;
loading the cell-delay ML model configuration files to form a cell-delay inference core;
performing operations of the cell-delay inference core using the extracted cell-delay feature values as input to calculate predicted cell-delay values; and
iterating the user design by an ML design flow tools responsive to the predicted slew-rate values, the predicted net-delay values and the predicted cell-delay values until a final user design is obtained that is free of timing violations.
2. The method of claim 1 wherein the loading slew-rate ML model configuration files of the slew-rate ML model to form the slew-rate inference core further comprises loading the slew-rate ML model configuration files into a neural network engine, the neural network engine operable for performing operations of the slew-rate inference core using the obtained slew-rate feature values as input to calculate the predicted slew-rate values.
3. The method of claim 1 further comprising programming the final user design into a target field programmable gate array integrated circuit device.
4. The method of claim 1 further comprising generating a plurality of photomasks corresponding to the final user design.
5. The method of claim 1 further comprising:
sending the predicted slew-rate values to the ML design flow tools;
sending the predicted net-delay values to the ML design flow tools; and
sending the predicted cell-delay values to the ML design flow tools.
6. The method of claim 1 further comprising:
generating the slew-rate ML model, the net-delay ML model and the cell-delay ML model.
7. The method of claim 6 further comprising:
receiving input indicating features of integrated circuit designs and the architecture of the slew-rate ML model, the net-delay ML model and the cell-delay ML model; and
receiving Existing Reference-Design (ERD) examples,
wherein:
generating the slew-rate ML model comprises extracting ERD slew-rate feature values from the ERD examples, computing ERD slew-rate true labels corresponding to the extracted ERD slew-rate feature values and performing training, validation and testing of the generated slew-rate ML model using the extracted ERD slew-rate feature values and corresponding ERD slew-rate true labels;
generating the net-delay ML model comprises extracting ERD net-delay feature values from the ERD examples, computing ERD net-delay true labels corresponding to the extracted ERD net-delay feature values, and performing training, validation and testing of the generated net-delay ML model using the extracted ERD net-delay feature values and corresponding ERD net-delay true labels; and
generating the cell-delay ML model comprises extracting ERD cell-delay feature values from the ERD examples, computing ERD cell-delay labels corresponding to the extracted ERD cell-delay feature values and performing training, validation and testing of the generated cell-delay ML model using the extracted ERD cell-delay feature values and corresponding ERD cell-delay labels.
8. The method of claim 7 wherein the validation of the slew-rate ML model, the net-delay ML model and the cell cell-delay ML model further comprises:
performing a first validation to identify a first-time-validated ML model;
determining if the first-time-validated ML model meets predetermined criteria;
if the first-time-validated ML model meets the predetermined criteria, proceeding to test the first-time-validated ML model; and
identifying each first-time-validated ML model that fails to meet the predetermined criteria as a failed ML model and modifying the failed ML model so that it meets the predetermined criteria.
9. The method of claim 8 wherein the modifying the failed ML model further comprises:
determining whether the failed ML model has failed for a first time;
if the failed ML model has failed for a first time, extracting values for an additional feature for the first-failed ML model, updating the first-failed ML model to account for the additional feature, re-training the first-failed ML model and re-validating the first-failed ML model; and
if the ML model has failed more than once, adding additional training data to the training data set of the failed ML model from new sets of ERD examples to generate an updated training data set, re-training the failed ML model using its updated training data set, and re-validating the failed ML model.
10. An integrated circuit design system with delay verification using an interference core, comprising:
a data storage to store configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model;
a user-design feature extractor coupled to the data storage, the user-design feature extractor to extract slew-rate feature values, net-delay feature values, and cell-delay feature values from a user design;
ML design flow tools coupled to the user-design feature extractor and to the data storage; and
a prediction ML module coupled to the data storage, the user-design feature extractor, and the ML design flow tools, the prediction ML module configured to:
load the slew-rate ML model configuration files to form a slew-rate inference core, load the net-delay ML model configuration files to form a net-delay inference core and load the cell-delay ML model configuration files to form a cell-delay inference core,
perform operations of the slew-rate inference core using the extracted slew-rate feature values as input to calculate predicted slew-rate values, perform operations of the net-delay inference core using the extracted net-delay feature values as input to calculate predicted net-delay values and perform operations of the cell-delay inference core using the extracted cell-delay feature values as input to calculate predicted cell-delay values, and
send the predicted slew-rate values, the predicted net-delay values and the predicted cell-delay values to the ML design flow tools,
wherein the ML design flow tools are configured to iterate the user design responsive to the predicted slew-rate values, the predicted net-delay values and predicted cell-delay values until the user design is free of timing violations to identify a final user design.
11. The integrated circuit design system with delay verification using an interference core of claim 10 further comprising:
One or more input to receive input indicating features of integrated circuit designs, to receive the architecture of the slew-rate ML model, the net-delay ML model and the cell-delay ML model, and to receive existing reference-design (ERD) examples;
an ERD feature extractor coupled to the input, the ERD feature extractor configured to extract ERD feature values from the received ERD examples to obtain ERD slew-rate feature values, ERD net-delay feature values and ERD cell-delay feature values;
design flow tools coupled to the ERD feature extractor, the design flow tools to compute ERD slew-rate true labels corresponding to the extracted ERD slew-rate feature values, compute ERD net-delay true labels corresponding to the extracted ERD net-delay feature values and compute ERD cell-delay true labels corresponding to the extracted ERD cell-delay feature values;
a training, validation and testing ML module configured to:
generate a slew-rate ML model and perform training, validation and testing using the extracted ERD slew-rate feature values and corresponding ERD slew-rate true labels;
generate a net-delay ML model and perform training, validation and testing using the extracted ERD net-delay feature values and corresponding ERD net-delay true labels; and
generate a cell-delay ML model and perform training, validation and testing using the extracted ERD cell-delay feature values and corresponding ERD cell-delay true labels.
12. The integrated circuit design system with delay verification using an interference core of claim 10 further comprising at least one of a device programmer or a mask generator coupled to the ML design flow tools.
13. A method for integrated circuit design with delay verification comprising:
receiving input indicating features of integrated circuit designs and an architecture of a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model;
receiving Existing Reference-Design (ERD) examples;
generating the slew-rate ML model by extracting ERD slew-rate feature values from the ERD examples, computing ERD slew-rate true labels corresponding to the extracted ERD slew-rate feature values, and performing training, validation and testing of the generated slew-rate ML model using the extracted ERD slew-rate feature values and corresponding ERD slew-rate true labels;
generating the net-delay ML model by extracting ERD net-delay feature values from the ERD examples, computing ERD net-delay true labels corresponding to the extracted ERD net-delay feature values, and performing training, validation and testing of the generated net-delay ML model using the extracted ERD net-delay feature values and corresponding ERD net-delay true labels;
generating the cell-delay ML model by extracting ERD cell-delay feature values from the ERD examples, computing ERD cell-delay labels corresponding to the extracted ERD cell-delay feature values, and performing training, validation and testing of the generated cell-delay ML model using the extracted ERD cell-delay feature values and corresponding ERD cell-delay labels;
storing configuration files for the generated slew-rate ML model, the net-delay ML model and the cell-delay ML model;
receiving a user design;
extracting values from the user design for each slew-rate feature, net-delay feature and cell-delay feature to obtain slew-rate feature values, net-delay feature values and cell-delay feature values;
loading the slew-rate ML model configuration files to form a slew-rate inference core;
performing operations of the slew-rate inference core using the extracted slew-rate feature values as input to calculate predicted slew-rate values;
loading the net-delay ML model configuration files to form a net-delay inference core;
performing operations of the net-delay inference core using the extracted net-delay feature values as input to calculate predicted net-delay values;
loading the cell-delay ML model configuration files to form a cell-delay inference core;
performing operations of the cell-delay inference core using the extracted cell-delay feature values as input to calculate predicted cell-delay values; and
iterating the user design responsive to the predicted slew-rate values, net-delay values and cell-delay values until a final user design is obtained that is free of timing violations.
14. The method of claim 13 wherein the training uses a random forest training algorithm.
15. The method of claim 13 further comprising:
dividing the extracted ERD slew-rate feature values and corresponding computed ERD slew-rate true labels into a slew-rate training data set, a slew-rate validation data set and a slew-rate test data set;
training the generated slew-rate ML model using the slew-rate training data set;
validating the generated slew-rate ML model using the slew-rate validation data set;
testing the generated slew-rate ML model using the slew-rate test data set; and
sending the predicted slew-rate values to design flow tools.
16. The method of claim 15 further comprising:
dividing the extracted ERD net-delay feature values and corresponding ERD net-delay true labels into a net-delay training data set, a net-delay validation data set and a net-delay test data set;
training the net-delay ML model using the net-delay training data set;
validating the net-delay ML model using the net-delay validation data set;
testing the net-delay ML model using the net-delay test data set; and
sending the predicted net-delay values to design flow tools.
17. The method of claim 16 further comprising:
dividing the extracted ERD cell-delay feature values and corresponding ERD cell-delay true labels into a cell-delay training data set, a cell-delay validation data set and a cell-delay test data set;
training the cell-delay ML model using the cell-delay training data set;
validating the cell-delay ML model using the cell-delay validation data set;
testing the cell-delay ML model using the cell-delay test data set; and
sending the predicted cell-delay values to design flow tools.