Output circuits for an analog neural memory system for deep learning neural network
Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.
1. An adaptable neuron circuit comprising:
a sample-and-hold circuit for sampling, in a first mode, a neuron current from a neuron in a neuromorphic memory array and storing a voltage on a gate of a transistor, and in a second mode, generating a mirrored current of the neuron current; and
a variable resistor for drawing the mirrored current during the second mode and generating an output voltage based on the mirrored current, the output voltage indicating a value stored in the neuron.
2. The adaptable neuron circuit of claim 1 , wherein the transistor is a PMOS transistor.
3. The adaptable neuron circuit of claim 1 , wherein the sample-and-hold circuit comprises a first switch, a second switch, and a third switch, and wherein in the first mode, the first switch is closed and couples the gate of the transistor to the neuron, the second switch is closed and couples the neuron to a source of the transistor, and the third switch is open.
4. The adaptable neuron circuit of claim 3 , wherein in the second mode, the first switch is open, the second switch is open, and the third switch is closed and couples the source of the transistor to the variable resistor.
5. A method comprising:
sampling, by a sample-and-hold circuit, a neuron current from a neuromorphic memory array and storing a voltage on a gate of a transistor;
generating, by the sample-and-hold circuit, a mirrored current of the neuron current; and
drawing, by a variable resistor, the mirrored current and generating an output voltage based on the mirrored current, the output voltage indicating a value stored in the neuron.
6. The method of claim 5 , wherein the transistor is a PMOS transistor.
7. The method of claim 5 , wherein the sample-and-hold circuit comprises a first switch, a second switch, and a third switch.
8. The method of claim 7 , wherein during the sampling, the first switch is closed and couples the gate of the transistor to the neuron, the second switch is closed and couples the neuron to a source of the transistor, and the third switch is open.
9. The method of claim 7 , wherein during the generating, the first switch is open, the second switch is open, and the third switch is closed and couples the source of the transistor to the variable resistor.