Low cost cryptographic accelerator
A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.
1. A hardware cryptographic accelerator, comprising:
an interface to:
receive cryptographic data; and
decode an address received with the cryptographic data via an aliased register map for the cryptographic accelerator, the decoded address indicating a cryptographic operation; and
associate the cryptographic data with a cryptographic process to perform the cryptographic operation indicated by the decoded address on the cryptographic data;
a transformation logic to perform the cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic to perform cryptographic operations for a plurality of different cryptographic processes; and
a state register to store a result of the cryptographic operation.
2. The hardware cryptographic accelerator of claim 1 , wherein the cryptographic process is from a group of cryptographic processes comprising: Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA) or Galois Counter Mode (GCM).
3. The hardware cryptographic accelerator of claim 1 , comprising a command register to store the decoded address and for controlling the cryptographic operation.
4. The hardware cryptographic accelerator of claim 1 , wherein the cryptographic process is AES, and the cryptographic operation includes calculating round keys using a key schedule.
5. The hardware cryptographic accelerator of claim 1 , wherein the cryptographic process is AES and the cryptographic operation is one of: SubBytes, Inverse SubBytes, ShiftRows, Inverse ShiftRows, MixColumn or Inverse MixColumn operation.
6. The hardware cryptographic accelerator of claim 1 , wherein the cryptographic process is SHA and the cryptographic operation is one of: Message Expansion loop and Compression Function loop.
7. The hardware cryptographic accelerator of claim 1 , wherein the cryptographic process is GCM and the cryptographic operation is a finite field multiplication in GF (2 128 ).
8. The hardware cryptographic accelerator of claim 1 , wherein the interface to receive the cryptographic data responsive to the cryptographic data being written from a central-processing unit (CPU) register to the state register during write cycle.
9. The hardware cryptographic accelerator of claim 8 , wherein the cryptographic data is transformed in the cryptographic accelerator during the write cycle before being written to the state register.
10. A method of accelerating a cryptographic process by a hardware accelerator, the method comprising:
receiving a cryptographic data;
decoding an address received with the cryptographic data responsive to an aliased register map of the hardware accelerator, the decoded address indicating a cryptographic operation;
associating the cryptographic data with a cryptographic process to perform the cryptographic operation indicated by the decoded address on the cryptographic data;
performing the cryptographic operation on the cryptographic data according to the cryptographic process; and
obtaining transformed cryptographic data responsive to performing the cryptographic operation.
11. The method of claim 10 , comprising:
associating the cryptographic data with the cryptographic operation responsive to decoding the address received with the cryptographic data.
12. The method of claim 10 , wherein the cryptographic process is from a group of cryptographic processes comprising: Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA) or Galois Counter Mode (GCM).
13. The method of claim 10 , wherein the performing the cryptographic operation on the cryptographic data according to the cryptographic process comprises performing the cryptographic operation on the cryptographic data according to the cryptographic process responsive to a control signal stored at a command register of the hardware accelerator.
14. The method of claim 10 , wherein the performing the cryptographic operation according to the cryptographic process comprises calculating round keys using a key schedule.
15. The method of claim 10 , wherein the performing the cryptographic operation according to the cryptographic process comprises performing one of: SubBytes, Inverse SubBytes, ShiftRows, Inverse ShiftRows, MixColumn or Inverse MixColumn operation.
16. The method of claim 10 , wherein the performing the cryptographic operation according to the cryptographic process comprises performing one of: Message Expansion loop and Compression Function loop.
17. The method of claim 10 , wherein the performing the cryptographic operation according to the cryptographic process comprises performing a finite field multiplication in GF (2 128 ).
18. The method of claim 10 , wherein the receiving a cryptographic data comprises: receiving the cryptographic data at a state register of the hardware accelerator.