Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals
An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW 2 N).
1. A method of forming an integrated circuit structure, comprising:
forming a plurality of metal structures in a metal layer, the plurality of metal structures defining a pair of metal e-fuse terminals and a metal interconnect element spaced apart from the pair of metal e-fuse terminals;
depositing a single conductive e-fuse/barrier layer on the plurality of metal structures, the single conductive e-fuse/barrier layer comprising a conductive material that provides a barrier against metal diffusion; and
patterning the single conductive e-fuse/barrier layer to define:
(a) an e-fuse element defined by a first portion of the single conductive e-fuse/barrier layer in contact with the pair of metal e-fuse terminals, the e-fuse element providing a conductive path between the metal e-fuse terminals through the e-fuse element to define an e-fuse module; and
(b) an interconnect diffusion barrier region defined by a second portion of the single conductive e-fuse/barrier layer located on the metal interconnect element, the second portion of the single conductive e-fuse/barrier layer being physically distinct from the first portion of the single conductive e-fuse/barrier layer;
wherein the single conductive e-fuse/barrier layer defines both the e-fuse element and the interconnect diffusion barrier region; and
depositing a dielectric layer directly on at least the first portion of the single conductive e-fuse/barrier layer defining the e-fuse element.
2. The method of claim 1 , wherein the single conductive e-fuse/barrier layer comprises TiW or TiW 2 N.
3. The method of claim 1 , wherein the single conductive e-fuse/barrier layer comprises NiCr, TiN, or TaN.
4. The method of claim 1 , wherein forming the plurality of metal structures in the metal layer comprises forming a plurality of copper trench elements in a copper interconnect layer.
5. The method of claim 1 , wherein forming the plurality of metal structures in the metal layer comprises forming a plurality of copper damascene structures.
6. The method of claim 1 , wherein depositing the dielectric layer directly on at least the first portion of the single conductive e-fuse/barrier layer comprises forming a dielectric barrier layer directly on at least the first portion of the single conductive e-fuse/barrier layer before patterning the single conductive e-fuse/barrier layer; and
wherein patterning the single conductive e-fuse/barrier layer comprises patterning the dielectric barrier layer together with the single conductive e-fuse/barrier layer.
7. The method of claim 1 , wherein depositing the dielectric layer directly on at least the first portion of the single conductive e-fuse/barrier layer comprises forming a dielectric barrier layer directly on at least the first portion of the single conductive e-fuse/barrier layer after patterning the single conductive e-fuse/barrier layer.
8. The method of claim 1 , wherein depositing the dielectric layer directly on at least the first portion of the single conductive e-fuse/barrier layer comprises forming a dielectric barrier layer comprising SiC or SiN directly on at least the first portion of the single conductive e-fuse/barrier layer.
9. The method of claim 1 , wherein the single conductive e-fuse/barrier layer consists of either TiW or TiW 2 N.
10. The method of claim 1 , wherein depositing the dielectric layer directly on at least the first portion of the single conductive e-fuse/barrier layer comprises forming a dielectric region over the e-fuse module and over the metal interconnect element; and
the method comprises forming an interconnect via in the dielectric region, the interconnect via conductively connected to the metal interconnect element.
11. A method of forming an integrated circuit structure, comprising:
forming a plurality of metal structures in a metal layer, the plurality of metal structures defining a pair of metal e-fuse terminals and a metal interconnect element spaced apart from the pair of metal e-fuse terminals;
depositing a single conductive e-fuse/barrier layer on the plurality of metal structures, the single conductive e-fuse/barrier layer comprising a conductive material that provides a barrier against metal diffusion; and
patterning the single conductive e-fuse/barrier layer to define:
(a) an e-fuse element defined by a first portion of the single conductive e-fuse/barrier layer in contact with the pair of metal e-fuse terminals, with no other conductive layer formed on the first portion of the single conductive e-fuse/barrier layer, wherein the e-fuse element fully covers a top surface of both metal e-fuse terminals to provide a barrier against metal diffusion from the metal e-fuse terminals, and wherein the e-fuse element provides a conductive path between the metal e-fuse terminals through the e-fuse element to define an e-fuse module; and
(b) an interconnect diffusion barrier region defined by a second portion of the single conductive e-fuse/barrier layer located on the metal interconnect element, the second portion of the single conductive e-fuse/barrier layer being physically distinct from the first portion of the single conductive e-fuse/barrier layer;
such that the same conductive material of the single conductive e-fuse/barrier layer defines both the e-fuse element and the interconnect diffusion barrier region.
12. The method of claim 11 , wherein the interconnect diffusion barrier region fully covers a top surface of the metal interconnect element to provide a barrier against metal diffusion from the metal interconnect element.