Analog neural memory array in artificial neural network with source line pulldown mechanism
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.
1. A non-volatile memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns;
a bit line switch on a first side of the array;
a pulldown bitline switch on a second side of the array opposite the first side;
a bit line coupled to the bit line switch and to a column of non-volatile memory cells in the array; and
a pulldown bitline coupled to the pulldown bitline switch and to a pulldown cell adjacent to a cell in the column of non-volatile memory cells in the array;
wherein during a read, verify, or erase operation of a selected non-volatile memory cell in the column and comprising a bit line terminal and a source line terminal, current flows: (i) through the bit line into the bit line terminal of the selected non-volatile memory cell, (ii) out of the source line terminal of the selected non-volatile memory cell into a source line, (iii) into a source line terminal of the pull down cell, and (iv) through a bit line terminal of the pull down cell into the pulldown bit line.
2. The non-volatile memory system of claim 1 , wherein the pulldown cell has the same physical structure as the selected memory cell.
3. The non-volatile memory system of claim 1 , wherein the array of non-volatile memory cells arranged in rows and columns is part of a neural network.
4. The non-volatile memory system of claim 3 , wherein the neural network is an analog neural network.
5. The non-volatile memory system of claim 1 , wherein the pulldown cell has a wider diffusion area than the selected non-volatile memory cell.
6. The non-volatile memory system of claim 1 , wherein the pulldown cell has a bias condition different than a bias condition of the selected non-volatile memory cell.
7. The non-volatile memory system of claim 1 , wherein the array comprises rows consisting entirely of pulldown cells.
8. The non-volatile memory system of claim 1 , wherein the array comprises a plurality of sets of four rows, wherein each of the plurality of sets comprises two adjacent rows of pulldown cells.
9. The non-volatile memory system of claim 1 , wherein the rows of the array comprise alternating rows of data cells and pulldown cells.
10. The non-volatile memory system of claim 1 , wherein the non-volatile cells in the array of non-volatile memory cells are split-gate non-volatile memory cells.
11. The non-volatile memory system of claim 1 , wherein the non-volatile cells in the array of non-volatile memory cells are stacked-gate non-volatile memory cells.
12. A non-volatile memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns;
a plurality of bit line switches on a first side of the array;
a plurality of pulldown bitline switches on a second side of the array opposite the first side;
a plurality of bit lines coupled to respective columns of non-volatile memory cells in the array and to respective bit line switches; and
a plurality of pulldown bitlines coupled to respective pulldown cells in the array and to respective pulldown bitline switches;
wherein during a read, verify, or erase operation of a selected non-volatile memory cell in the array, current flows: (i) through one of the plurality of bit lines into the bit line terminal of the selected non-volatile memory cell, (ii) out of the source line terminal of the selected non-volatile memory cell into a source line, (iii) into source line terminals of the pull down cells, and (iv) through bit line terminals of the pull down cells into the plurality of pulldown bit lines.
13. The non-volatile memory system of claim 12 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate non-volatile memory cells.
14. The non-volatile memory system of claim 12 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate non-volatile memory cells.
15. The non-volatile memory system of claim 12 , wherein the pulldown cells have the same physical structure as the non-volatile memory cells.
16. The non-volatile memory system of claim 12 , wherein at least one column of the array consists entirely of pulldown cells.
17. The non-volatile memory system of claim 12 , wherein at least one row of the array consists entirely of pulldown cells.
18. The non-volatile memory system of claim 12 , wherein the memory system is part of a neural network.
19. The non-volatile memory system of claim 18 , wherein the neural network is an analog neural network.