Temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array
Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
1. A method of compensating for temperature changes in an array of memory cells, the method comprising:
determining, using a temperature sensor, an operating temperature in the array of memory cells:
generating, by a controller, a set of bits in response to the operating temperature;
generating, by a circuit, a bias voltage in response to the set of bits; and
applying the bias voltage to a gate of a selected memory cell in the array of memory cells to compensate for the change in the operating temperature.
2. The method of claim 1 , wherein the array of memory cells is part of a neural network.
3. The method of claim 2 , wherein the array of memory cells is a vector-by-matrix multiplication array.
4. The method of claim 1 , wherein the memory cells in the array of memory cells are non-volatile memory cells.
5. The method of claim 4 , wherein the non-volatile memory cells are split-gate flash memory cells.
6. The method of claim 4 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
7. An analog memory system, comprising:
an array of memory cells;
a temperature sensor to determine an operating temperature in the array of memory cells;
a controller to generate a set of bits in response to the operating temperature; and
a circuit to generate a bias voltage in response to the set of bits and to apply the bias voltage to a gate of a selected memory cell in the array of memory cells to compensate for the change in the operating temperature.
8. The analog memory system of claim 7 , wherein the memory cells in the array of memory cells are non-volatile memory cells.
9. The analog memory system of claim 8 , wherein the non-volatile memory cells are split-gate flash memory cells.
10. The analog memory system of claim 8 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
11. The analog memory system of claim 7 , wherein the array of memory cells is part of a neural network.
12. The analog memory system of claim 7 , wherein the array of memory cells is a vector-by-matrix multiplication array.