Analog neural memory array in artificial neural network comprising logical cells and improved programming mechanism
Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.
1. A memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns;
a logical cell comprising one or more non-volatile memory cells configured as coarse cells and one or more non-volatile memory cells configured as fine cells located in the same row of the array; and
a tuning cell.
2. The memory system of claim 1 , wherein the system is configured to program coarse cells using a coarse programming method and to program fine cells using a fine programming method.
3. The memory system of claim 1 , wherein each of the non-volatile memory cells configured as coarse cells has a range of possible programmed current values that is greater than a range of possible programmed current values of each of the non-volatile memory cells configured as fine cells.
4. The memory system of claim 1 , wherein the tuning cell is used to tune an adjacent cell next to it.
5. The memory system of claim 4 , wherein the tuning cell is used to tune the adjacent cell through coupling between a floating gate of the tuning cell and a floating gate of the adjacent cell.
6. The memory system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.
7. The memory system of claim 1 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
8. The memory system of claim 1 , wherein each row comprises one or more isolation cells.
9. The memory system of claim 8 , wherein the isolation cells are programmed, partially programmed, erased, partially erased, or in a native state.
10. The memory system of claim 8 , wherein the isolation cells are dummy cells.
11. The memory system of claim 1 , wherein each row comprises one or more strap cells.
12. The memory system of claim 11 , wherein the strap cells are dummy cells.
13. A memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns; and
a logical cell comprising one or more non-volatile memory cells configured as coarse cells, one or more non-volatile memory cells configured as fine cells located in the same row of the array, and one or more tuning cells in the same row of the array, and wherein during a programming operation of the logical cell, the one or more tuning cells are programmed.
14. The memory system of claim 13 , wherein the one or more tuning cells in the logical cell are adjacent to a coarse cell in an adjacent logical cell.
15. A memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns; and
a logical cell comprising one or more non-volatile memory cells configured as coarse cells and one or more non-volatile memory cells configured as fine cells located in the same row of the array;
wherein the logical cell is located: (i) in a row between two or more isolation cells, (ii) in a row between two or more strap cells, or (iii) in a row between two or more source line pulldown cells.
16. A memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns; and
a logical cell comprising one or more non-volatile memory cells configured as coarse cells and one or more non-volatile memory cells configured as fine cells located in the same row of the array;
wherein the memory system is part of a neural network.
17. The memory system of claim 16 , wherein the neural network is an analog neural network.
18. A method of programming a logical cell comprising one or more non-volatile memory cells configured as coarse cells, one or more non-volatile memory cells configured as fine cells located in a row of an array of non-volatile memory cells, and one or more non-volatile memory cells configured as tuning cells in the same row, the method comprising:
programming the one or more non-volatile memory cells configured as coarse cells using a coarse programming method;
programming the one or more non-volatile memory cells configured as fine cells using a fine programming method; and
programming the one or more non-volatile memory cells configured as tuning cells using a tuning method.
19. The method of claim 18 , further comprising:
verifying a value programmed in the logical cell.
20. The method of claim 18 , wherein the non-volatile memory cells are split-gate flash memory cells.
21. The method of claim 18 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
22. The method of claim 18 , wherein the logical cell is located in a row between two or more isolation cells.
23. The method of claim 18 , wherein the logical cell is located in a row between two or more strap cells.
24. The method of claim 18 , wherein the logical cell is located in a row between two or more source line pulldown cells.
25. A method of programming a logical cell comprising one or more non-volatile memory cells configured as coarse cells and one or more non-volatile memory cells configured as fine cells located in a row of an array of non-volatile memory cells, the method comprising:
programming the one or more non-volatile memory cells configured as coarse cells using a coarse programming method; and
programming the one or more non-volatile memory cells configured as fine cells using a fine programming method;
wherein the logical cell is part of a neural network.
26. The method of claim 25 , wherein the neural network is an analog neural network.
27. A memory system, comprising:
an array of memory cells arranged in rows and columns; and
a logical cell comprising one or more memory cells configured as coarse cells and one or more memory cells configured as fine cells located in the same row of the array; and
a tuning cell.