IP Library Granted Patent US 11,308,023
Granted Patent B2
US 11,308,023 · App. 17/109,315 · Granted Apr 19, 2022

Method and system for enhanced SPI communication

Inventors: Jason Remple (San Diego, CA); Andrea Panigada (San Diego, CA); Bogdan Bolocan (Eggenstein-Leopoldshafen, DE)
Assignee: Microchip Technology Incorporated
G06F13/4291G06F9/30101G06F13/362G06F13/374
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Quick Facts
Patent No.
US 11,308,023
App. No.
17/109,315
Granted
Apr 19, 2022
Kind
B2
Abstract

A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

Claims (29)

1. A slave device comprising a serial peripheral interface (SPI) module, further comprising a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device, wherein the slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device, wherein the mode detection circuit comprises an edge and signal detection circuit receiving a chip select signal and a clock signal from the master device.

2. The slave device according to claim 1 , wherein the edge and signal detection circuit evaluates the state of the clock signal when the chip select signal transitions from an asserted state to an idle state.

3. The slave device according to claim 1 , wherein a first mode is a functional mode and wherein receiving signals from the master device indicating the first mode control a primary function of the slave device.

4. A slave device comprising a serial peripheral interface (SPI) module, further comprising a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device, wherein the slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device, wherein the slave device is an analog-to-digital converter and the first mode is a conversion mode.

5. The slave device according to claim 4 , wherein selecting a first SPI operating mode by the master device triggers a start of at least one conversion of the analog-to-digital converter.

6. A slave device comprising a serial peripheral interface (SPI) module, further comprising a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device, wherein the slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device, wherein a second mode is a command mode that allows configuration of the slave device and access to registers of the slave device.

7. The slave device according to claim 6 , wherein after identifying the second mode by the slave device, the slave device is configured to expect a command on a data in signal line.

8. The slave device according to claim 6 , wherein the slave device is further configurable to operate in a Single mode or a Daisy-Chain mode, wherein a mode switch is performed through a dedicated command.

9. The slave device according to claim 8 , wherein a received command is evaluated by the slave device as soon as a last bit of the command is received when in Single mode and wherein in Daisy-Chain mode a received command is evaluated by the slave device only after de-assertion of a chip select signal.

10. A slave device comprising a serial peripheral interface (SPI) module, further comprising a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device, wherein the slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device, wherein the slave device is further configurable to operate in a third mode through a logic state on a data output line of the master device, wherein the third mode is a command mode in a Daisy-Chain mode.

11. A system comprising a master device and a plurality of slave devices coupled in daisy-chain topology with a serial peripheral interface (SPI) module of the master device, wherein each slave device comprises an SPI module and further comprises a mode detection circuit configured to detect an SPI operating mode that has been applied by the master device, wherein each slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device through a clock signal and a chip select signal.

12. The system according to claim 11 , wherein a first mode is a functional mode wherein a primary function of the slave device is performed and wherein a second mode is a command mode that allows configuration of the slave device and access to registers of the slave device.

13. The system according to claim 12 , wherein a dedicated command received by a slave device in command mode causes the device to enter a Daisy-Chain mode.

14. The system according to claim 12 , wherein when in Daisy-Chain mode, each slave device only evaluates a received command if the master de-asserts the chip select signal while remaining in command mode.

15. A method of operating a slave device coupled with a master device through a serial peripheral interface (SPI) module, the method comprising:

detecting an SPI operating mode by the slave device that has been applied by a master device, wherein the slave device is configurable to operate in a first or a second mode, by

receiving and analyzing a chip select signal and a clock signal from the master device to determine whether said first or second mode has been applied; and

operating the slave device in the first or second mode depending on the detection of the SPI operating mode as applied by the master device.

16. The method according to claim 15 , wherein the state of the clock signal is evaluated when the chip select signal transitions from an asserted state to an idle state.

17. A method of operating a slave device coupled with a master device through a serial peripheral interface (SPI) module, the method comprising:

detecting and SPI operating mode by the slave device that has been applied by a master device, wherein the slave device is configurable to operate in a first or a second mode, and

operating the slave device in the first or second mode depending on the detection of the SPI operating mode as applied by the master device, wherein a first mode is a functional mode wherein a primary function of the slave device is performed and wherein a second mode is a command mode that allows configuration of the slave device and access to registers of the slave device.

18. The method according to claim 17 , further comprising:

configuring the slave device to operate in a Single mode or a Daisy-Chain mode, wherein a mode switch is performed through a dedicated command received during a command mode.

19. A method for operating a system comprising a master device and a plurality of slave devices coupled in daisy-chain topology with a serial peripheral interface (SPI) module of the master device, wherein each slave device comprises an SPI module and further comprises a mode detection circuit configured to detect an SPI operating mode that has been applied by the master device, the method comprising:

sending signals through the SPI module by the master device that indicate a selected SPI operating mode; and

receiving in Daisy-Chain fashion by each slave device said signals and determining by each slave device to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

20. The method according to claim 19 , wherein a dedicated command received by a slave device in command mode causes the device to enter a Daisy-Chain mode.

21. The method according to claim 19 , wherein when in Daisy-Chain mode, each slave device only evaluates a received command if the master de-asserts a chip select signal while remaining in command mode.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2020
From: REMPLE, JASON; PANIGADA, ANDREA; BOLOCAN, BOGDAN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 054513/0915 →
Continuity (2)
Provisional Application 62993959 · Mar 24, 2020
Related Publication 20210303503A1 · Sep 30, 2021