IP Library Granted Patent US 11,652,162
Granted Patent B2
US 11,652,162 · App. 17/021,678 · Granted May 16, 2023

Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps

Inventors: Feng Zhou (Fremont, CA); Xian Liu (Sunnyvale, CA); Chien-Sheng Su (Saratoga, CA); Nhan Do (Saratoga, CA); Chunming Wang (Shanghai, CN)
Assignee: Silicon Storage Technology, Inc.
H01L29/66825H01L27/0705H01L28/00H01L29/0847H01L29/40114H01L29/42328H01L29/66545H01L29/788G11C2216/10H01L29/6653
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Quick Facts
Patent No.
US 11,652,162
App. No.
17/021,678
Granted
May 16, 2023
Kind
B2
Abstract

A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).

Claims (26)

1. A method of forming a non-volatile memory cell comprising:

forming a first insulation layer on a semiconductor substrate;

forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process;

forming an insulation block on the first polysilicon layer, the insulation block having a first side and a second side;

forming insulation spacers adjacent the first and second sides;

reducing a width of the insulation spacer adjacent the first side;

removing portions of the first polysilicon layer while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block and the insulation spacers adjacent the first and second sides of the insulation block;

forming a source region in the substrate adjacent the first side of the insulation block;

removing the insulation spacers to expose end portions of the polysilicon block of the first polysilicon layer;

forming a layer of insulation material that at least extends along the exposed end portions of the polysilicon block of the first polysilicon layer;

forming a second polysilicon layer over the substrate and the insulation block in a second polysilicon deposition process;

removing portions of the second polysilicon layer while maintaining a first polysilicon block and a second polysilicon block of the second polysilicon layer, wherein:

the first polysilicon block of the second polysilicon layer is disposed adjacent the first side of the insulation block and over the source region,

the second polysilicon block of the second polysilicon layer is disposed adjacent the second side of the insulation block; and

forming a drain region in the substrate adjacent the second polysilicon block of the second polysilicon layer

wherein:

the first polysilicon block of the second polysilicon layer includes a first portion laterally adjacent to the polysilicon block of the first polysilicon layer, and a second portion that extends up and over the polysilicon block of the first polysilicon layer;

the second polysilicon block of the second polysilicon layer includes a first portion laterally adjacent to the polysilicon block of the first polysilicon layer, and a second portion that extends up and over the polysilicon block of the first polysilicon layer.

2. The method of claim 1 , wherein an amount of vertical overlap between the first polysilicon block of the second polysilicon layer and the polysilicon block of the first polysilicon layer is less than an amount of vertical overlap between the second polysilicon block of the second polysilicon layer and the polysilicon block of the first polysilicon layer.

3. The method of claim 1 , wherein the insulation block is formed of nitride, oxide, or a composite of layers including both oxide and nitride.

4. The method of claim 1 , wherein the first insulation layer is formed of oxide or nitrogen treated oxide.

5. The method of claim 1 , further comprising:

removing the second polysilicon block of the second polysilicon layer; and

forming a metal block adjacent the second side of the insulation block.

6. The method of claim 5 , further comprising:

forming a layer of high-K insulation material between the metal block and the second side of the insulation block.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →