Precise data tuning method and apparatus for analog neural memory in an artificial neural network
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
1. A system comprising:
a vector-by-matrix multiplication array of non-volatile memory cells, wherein a weight value w is stored as a differential pair w+ and w− in a first non-volatile memory cell and a second non-volatile memory cell in the array according to the formula w=(w+)−(w−), where w+ includes a non-zero offset value and w− includes the non-zero offset value.
2. The system of claim 1 , wherein the non-zero offset value is a positive value.
3. The system of claim 1 , wherein the non-zero offset value is a negative value.
4. The system of claim 1 , wherein when a value of 0 is desired for w, a value equal to the non-zero offset value is stored for w+ and w−.
5. The system of claim 1 , wherein when a value of 0 for w is indicated by a stored value for w less than a predetermined threshold.
6. The system of claim 5 , wherein the predetermined threshold is 5 nA.
7. The system of claim 5 , wherein the predetermined threshold is 10 nA.
8. The system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.
9. The system of claim 1 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
10. The system of claim 1 , wherein the first non-volatile memory cell is tuned to w+ by one or more of a coarse, fine, or ultra fine tuning algorithm and the second non-volatile memory cell is tuned to w− by one or more of a fine or ultra fine tuning algorithm.
11. A system comprising:
a vector-by-matrix multiplication array of non-volatile memory cells, the array organized into rows and columns of non-volatile memory cells, wherein a weight value w is stored as a differential pair w+ and w− in a first non-volatile memory cell and a second non-volatile memory cell according to the formula w=(w+)−(w−), where the number of stored w+ and w− values per column is approximately equal for all columns in the array.
12. The system of claim 11 , wherein within each differential pair, w+ includes a positive offset value and w− includes the positive offset value.
13. The system of claim 11 , wherein within each differential pair, w+ includes a negative offset value and w− includes the negative offset value.
14. The system of claim 11 , wherein when a value of 0 is desired for w, a value equal to the non-zero offset value is stored for w+ and w−.
15. The system of claim 11 , wherein when a value of 0 for w is indicated by a stored value for w less than a predetermined threshold.
16. The system of claim 15 , wherein the predetermined threshold is 5 nA.
17. The system of claim 15 , wherein the predetermined threshold is 10 nA.
18. The system of claim 11 , wherein the non-volatile memory cells are split-gate flash memory cells.
19. The system of claim 11 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
20. The system of claim 11 , wherein the first non-volatile memory cell is tuned to w+ by one or more of a coarse, fine, or ultra fine tuning algorithm and the second non-volatile memory cell is tuned by one or more of a fine or ultra fine tuning algorithm.
21. A method of programming, verifying, and reading a zero value in a differential pair of non-volatile memory cells in a vector-by-matrix multiplication array, the method comprising:
programming a first cell, w+, in the differential pair to a first current value;
verifying the first cell by applying a voltage to a control gate terminal of the first cell equal to a first voltage plus a bias voltage;
programming a second cell, w−, in the differential pair to the first current value;
verifying the second cell by applying a voltage to a control gate terminal of the second cell equal to the first voltage plus the bias voltage;
reading the first cell by applying a voltage to the control gate terminal of the first cell equal to the first voltage;
reading the second cell by applying a voltage to the control gate terminal of the second cell equal to the first voltage;
calculating a value w according to the formula w=(w+)−(w−).
22. The method of claim 21 , wherein the first cell is tuned by one or more of a coarse, fine, or ultra fine tuning algorithm and the second cell is tuned by one or more of a fine or ultra fine tuning algorithm.
23. A method of programming, verifying, and reading a zero value in a differential pair of non-volatile memory cells in a vector-by-matrix multiplication array, the method comprising:
programming a first cell, w+, in the differential pair to a first current value;
verifying the first cell by applying a voltage to a control gate terminal of the first cell equal to a first voltage plus a bias voltage;
programming a second cell, w−, in the differential pair to the first current value;
verifying the second cell by applying a voltage to a control gate terminal of the second cell equal to the first voltage plus the bias voltage;
reading the first cell by applying a voltage to the control gate terminal of the first cell equal to the first voltage;
reading the second cell by applying a voltage to the control gate terminal of the second cell equal to the first voltage;
calculating a value w according to the formula w=(w+)−(w−).
24. The method of claim 23 , wherein the first current value is a positive value.
25. The method of claim 23 , wherein the second current value is a negative value.
26. The method of claim 23 , wherein the first cell is tuned to w+ by one or more of a coarse, fine, or ultra fine tuning algorithm and the second cell is tuned to w− by one or more of a fine or ultra fine tuning algorithm.
27. A system comprising:
a vector-by-matrix multiplication array of non-volatile memory cells, the array organized into rows and columns of non-volatile memory cells, wherein a weight value w is stored as a differential pair w+ and w− according to the formula w=(w+)−(w−), wherein w+ is stored as a differential pair in a first non-volatile memory cell and a second non-volatile memory cell in the array and w− is stored as a differential pair in a third non-volatile memory cell and a fourth non-volatile memory cell in the array, wherein the storage of w+ is offset by a bias value and the storage of w− is offset by the bias value.
28. The system of claim 27 , wherein current range of the all memory cells is reduced approximately by memory cell current value representing bias value.
29. The system of claim 28 , wherein a bias value is shared across a number of memory cell levels.
30. The system of claim 27 , wherein the memory cell having number of current levels.
31. The system of claim 27 , wherein the bias value is a positive value.
32. The system of claim 27 , wherein the bias value is a negative value.
33. The system of claim 27 , wherein when a value of 0 is desired for w, a value equal to the bias value is stored for w+ and w−.
34. The system of claim 27 , wherein a value of 0 for w is indicated by a stored value for w less than a predetermined threshold.
35. The system of claim 34 , wherein the predetermined threshold is 5 nA.
36. The system of claim 34 , wherein the predetermined threshold is 10 nA.
37. The system of claim 27 , wherein the non-volatile memory cells are split-gate flash memory cells.
38. The system of claim 27 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
39. The system of claim 27 , wherein the first and third non-volatile memory cells are tuned by one or more of a coarse, fine, or ultra fine tuning algorithm and the second and fourth non-volatile memory cells are tuned by one or more of a fine or ultra fine tuning algorithm.
40. A system comprising:
a vector-by-matrix multiplication array of non-volatile memory cells, the array organized into rows and columns of non-volatile memory cells, wherein a weight value w is stored as a differential pair w+ and w− in a first non-volatile memory cell and a second non-volatile memory cell according to the formula w=(w+)−(w−), wherein values for w+ are selected from a first range of non-zero values and the values for w− are selected from a second range of non-zero values, wherein the first range and second range do not overlap.
41. The system of claim 40 , wherein a value of 0 for w is indicated by a stored value for w less than a predetermined threshold.
42. The system of claim 41 , wherein the predetermined threshold is 5 nA.
43. The system of claim 41 , wherein the predetermined threshold is 10 nA.
44. The system of claim 40 , wherein the non-volatile memory cells are split-gate flash memory cells.
45. The system of claim 40 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
46. The system of claim 40 , wherein the first non-volatile memory cell is tuned to w+ by one or more of a coarse, fine, or ultra fine tuning algorithm and the second non-volatile memory cell is tuned to w− by one or more of a fine or ultra fine tuning algorithm.
47. A method of operating a non-volatile memory cell in a vector-by-matrix multiplication array, the method comprising:
reading the non-volatile memory cell by applying a first bias voltage to a control gate of the non-volatile memory cell; and
applying a second bias voltage to the control gate of the non-volatile memory cell during one or more of a standby operation, a deep power down operation, or a testing operation.
48. The method of claim 47 , further comprising:
modulating a background data pattern or zero weight or non-user cells in the array.