Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network
Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.
1. A method of reading a selected non-volatile memory cell, the method comprising:
providing a plurality of input bits to an input circuit;
generating, by the input circuit, one or more input pulses in response to the plurality of input bits, where each value represented by the plurality of input bits results in generation of a different number of input pulses;
applying the input pulses to a terminal of the selected non-volatile memory cell;
receiving, by an output circuit, a plurality of output signals, each output signal received from a column containing the selected non-volatile memory cell in response to an input pulse in the one or more input pulses; and
summing the plurality of output signals to determine a value stored in the selected non-volatile memory cell.
2. The method of claim 1 , wherein each of the one or more input pulses has the same pulse width.
3. The method of claim 1 , wherein each output signal is weighted based on the binary bit location of the associated input bit.
4. The method of claim 1 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
5. The method of claim 4 , wherein the terminal is a control gate terminal.
6. The method of claim 1 , wherein the output circuit comprises an integrating analog-to-digital converter.
7. The method of claim 1 , wherein the output circuit comprises a successive approximation analog-to-digital converter.
8. The method of claim 1 , wherein the output circuit comprises a Sigma-Delta analog-to-digital converter.
9. The method of claim 1 , wherein the selected non-volatile memory cell is part of a neural network.
10. A method of reading a selected non-volatile memory cell, the method comprising:
providing a set of input bits to an input circuit;
sequentially applying, by the input circuit, an input signal to a terminal of the selected non-volatile memory cell for each input bit in the set of input bits;
sequentially receiving, by an output circuit, a plurality of output signals, each output signal received from a column containing the selected non-volatile memory cell in response to an input signal;
sequentially applying, by the output circuit, a binary weight to each output signal based on the binary location of the input bit within the set of input bits to generate a weighted output signal; and
summing, by the output circuit, the weighted output signals to determine a value stored in the selected non-volatile memory cell.
11. The method of claim 10 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
12. The method of claim 11 , wherein the terminal is a control gate terminal.
13. The method of claim 10 , wherein the output circuit comprises an integrating analog-to-digital converter.
14. The method of claim 10 , wherein the output circuit comprises a successive approximation analog-to-digital converter.
15. The method of claim 10 , wherein the output circuit comprises a Sigma-Delta analog-to-digital converter.
16. The method of claim 10 , wherein the selected non-volatile memory cell is part of a neural network.