Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
1. A method of programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than 2, the selected non-volatile memory cell comprising a floating gate and a control gate, the method comprising:
performing a coarse programming process comprising:
applying a programming voltage pulse to the control gate of the selected non-volatile memory cell;
repeating the applying step and increasing a duration of the programming voltage pulse each time the applying step is performed until a current through the selected non-volatile memory cell during a verify operation is less than or equal to a threshold current value; and
performing a precision programming process until a current through the selected non- volatile memory cell during a verify operation is less than or equal to a second threshold current value.
2. The method of claim 1 , further comprising:
performing a precision programming process until a current through the selected non-volatile memory cell during a verify operation is less than or equal to a third threshold current value.
3. The method of claim 2 , wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gate of the selected non-volatile memory cell.
4. The method of claim 2 , wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell.
5. The method of claim 1 , wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gate of the selected non-volatile memory cell.
6. The method of claim 1 , wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell.
7. The method of claim 1 , wherein the selected non-volatile memory cell comprises a floating gate.
8. The method of claim 7 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
9. The method of claim 1 , wherein the selected non-volatile memory cell is in a vector-by-matrix multiplication array in an analog memory deep neural network.
10. The method of claim 1 , further comprising:
before performing the coarse programming process:
programming the selected non-volatile memory cell to a ‘0’ state; and
erasing the selected non-volatile memory cell to a weakly-erased level.
11. The method of claim 1 , further comprising:
before performing the coarse programming process:
erasing the selected non-volatile memory cell to a ‘1’ state; and
programming the selected non-volatile memory cell to a weakly-programmed level.
12. The method of claim 1 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
integrating the current drawn by the selected non-volatile memory cell during the read operation using an integrating analog-to-digital converter to generate digital bits.
13. The method of claim 1 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
converting the current drawn by the selected non-volatile memory cell during the read operation into digital bits using a sigma delta analog-to-digital converter.
14. The method of claim 13 , wherein the selected non-volatile memory cell comprises a floating gate.
15. The method of claim 14 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
16. A method of programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than 2, the selected non-volatile memory cell comprising a floating gate and a control gate, the method comprising:
performing a coarse programming process comprising:
obtaining a threshold current value from a lookup table;
applying a programming voltage to the control gate of the selected non-volatile memory cell;
repeating the applying step and increasing the programming voltage by an incremental voltage each time the applying step is performed until a current through the selected non-volatile memory cell during a verify operation is less than or equal to the threshold current value; and
performing a precision programming process until a current through the selected non-volatile memory cell during a verify operation is less than or equal to a second threshold current value.
17. The method of claim 16 , further comprising:
performing a precision programming process until a current through the selected non-volatile memory cell during a verify operation is less than or equal to a third threshold current value.
18. The method of claim 17 , wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gate of the selected non-volatile memory cell.
19. The method of claim 17 , wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell.
20. The method of claim 16 , wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gate of the selected non-volatile memory cell.
21. The method of claim 16 , wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell.
22. The method of claim 16 , wherein the selected non-volatile memory cell is in a vector-by-matrix multiplication array in an analog memory deep neural network.
23. The method of claim 16 , further comprising:
before performing the coarse programming process:
programming the selected non-volatile memory cell to a ‘0’ state; and
erasing the selected non-volatile memory cell to a weakly-erased level.
24. The method of claim 16 , further comprising:
before performing the coarse programming process:
erasing the selected non-volatile memory cell to a ‘1’ state; and
programming the selected non-volatile memory cell to a weakly-programmed level.
25. The method of claim 16 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
integrating the current drawn by the selected non-volatile memory cell during the read operation using an integrating analog-to-digital converter to generate digital bits.
26. The method of claim 16 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
converting the current drawn by the selected non-volatile memory cell during the read operation into digital bits using a sigma delta analog-to-digital converter.