IP Library Patent Application 17233367
Patent Application
App. No. 17/233,367

ELECTRONIC FUSE (E-FUSE) WITH DISPLACEMENT-PLATED E-FUSE TERMINALS

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
17/233,367
Abstract

An electronic fuse (e-fuse) module may be formed in copper interconnect in an integrated circuit device. A pair of e-fuse terminals may be formed by forming a pair of spaced-apart e-fuse terminal structures (e.g., copper damascene structures) and forming a conductive barrier region on each e-fuse terminal structure. The barrier regions may be formed by displacement plating a conductive barrier layer, e.g., comprising CoWP, CoWB, Pd, CoP, Ni, Co, or Ni—Co alloy, on each e-fuse terminal structure. An e-fuse element, e.g., comprising NiCr, TiW, TiWN, or Al, may be formed on the barrier regions of the pair of e-fuse terminals to define a conductive path between the pair of e-fuse terminal structures through the e-fuse element and through the barrier region on each e-fuse terminal structure. The barrier regions may protect the e-fuse terminal structures (e.g., copper structures) from corrosion and/or diffusion.

Claims (27)

1 - 11 . (canceled)

12 . An integrated circuit structure, comprising:

an electronic fuse (e-fuse) module, comprising:

a pair of spaced-apart e-fuse terminals spaced apart from each other in a dielectric region, each of the e-fuse terminals comprising:

an e-fuse terminal structure formed in the dielectric region; and

a barrier region at a top of the e-fuse terminal structure;

an e-fuse element formed on the pair of spaced-apart e-fuse terminals to define a conductive path between the pair of e-fuse terminal structures through the e-fuse element and through the barrier region at the top of each metal e-fuse terminal structure.

13 . The integrated circuit structure of claim 12 , wherein the barrier region at the top of each e-fuse terminal structure comprises a displacement-plated barrier region.

14 . The integrated circuit structure of claim 12 , wherein the barrier region at the top of each e-fuse terminal structure comprises cobalt tungsten phosphide (CoWP).

15 . The integrated circuit structure of claim 12 , wherein the e-fuse terminal structures each comprise copper damascene structures.

16 . The integrated circuit structure of claim 12 , wherein the e-fuse element fully covers a top area of each e-fuse terminal.

17 . The integrated circuit structure of claim 12 , wherein the e-fuse element covers only a partial portion of a top area of each e-fuse terminal.

18 . The integrated circuit structure of claim 12 , wherein the e-fuse film includes (a) a pair of terminal regions, each covering a top area of one of the e-fuse terminals and (b) a connecting region connecting the pair of terminal regions, the connecting region having a smaller width than a width of each of the terminal regions.

19 . An integrated circuit structure, comprising:

an electronic fuse (e-fuse) module comprising:

a pair of spaced-apart e-fuse terminals, each comprising:

an e-fuse terminal structure formed in a first metal layer; and

a barrier region formed on the e-fuse terminal structure; and

an e-fuse element formed on the pair of spaced-apart e-fuse terminals to define a conductive path connecting the pair of e-fuse terminal structures through the e-fuse element and through the barrier region formed on each e-fuse terminal structure; and

an interconnect structure comprising:

an interconnect element formed in the first metal layer; and

a barrier region formed on the interconnect element.

20 . The integrated circuit structure of claim 19 , wherein the barrier region formed on each e-fuse terminal structure and the barrier region formed on the interconnect trench element each comprise a displacement-plated barrier region.

21 . The integrated circuit structure of claim 19 , wherein the barrier region formed on each e-fuse terminal structure and the barrier region formed on the interconnect trench element each comprise cobalt tungsten phosphide (CoWP).

22 . The integrated circuit structure of claim 19 , wherein the pair of e-fuse terminal structures and the interconnect trench element comprise copper damascene structures.

23 . The integrated circuit structure of claim 19 , further comprising an e-fuse film region formed on the barrier region formed on the interconnect trench element and spaced apart from the e-fuse element, wherein the e-fuse film region and the e-fuse element are formed from a common e-fuse film.

24 . The integrated circuit structure of claim 19 , wherein the e-fuse element comprises NiCr, TiW, TiWN, or Al.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059358/0398 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058213/0959 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2021
From: LENG, YAOJIAN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 056047/0877 →