Precision tuning of a page or word of non-volatile memory cells and associated high voltage circuits for an analog neural memory array in an artificial neural network
Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.
1. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising:
ramping up a voltage on control gate terminals of the word of non-volatile memory cells during a first time period;
ramping up a voltage on the source line terminal of the word of non-volatile memory cells during a second time period after the first time period; and
ramping up a voltage on the erase gate line terminal of the word of non-volatile memory cells during a third time period after the second time period.
2. The method of claim 1 , further comprising:
ramping down the voltage on the erase gate line terminals of the word of non-volatile memory cells during a fourth time period after the third time period;
ramping down the voltage on the source line terminals of the word of non-volatile memory cells during a fifth time period after the fourth time period; and
ramping down the voltage on control gate terminals of the word of non-volatile memory cells during a sixth time period after the fifth time period.
3. The method of claim 1 , wherein the array of non-volatile memory cells form an analog neural memory.
4. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a control gate terminal, a source line terminal and an erase gate terminal, the method comprising:
ramping up a control gate voltage on control gate terminals of the word of non-volatile memory cells to an intermediate voltage during a first time period;
ramping up a source line voltage on the source line terminal of the word of non-volatile memory cells during a second time period after the first time period;
ramping up an erase gate voltage on the erase gate line terminal of the word of non-volatile memory cells during a third time period after the second time period; and
ramping up the control gate voltage on control gate terminals of the word of non-volatile memory cells during a fourth time period after the third time period.
5. The method of claim 4 , further comprising:
ramping down the control gate voltage on control gate terminals of the word of non-volatile memory cells to an intermediate voltage during a fourth time period after the third time period;
ramping down the erase gate voltage on the erase gate line terminals of the word of non-volatile memory cells during a fifth time period after the fourth time period;
ramping down the source line voltage on the source line terminals of the word of non-volatile memory cells during a sixth time period after the fifth time period; and
ramping down the control gate voltage on control gate terminals of the word of non-volatile memory cells during a seventh time period after the sixth time period.
6. The method of claim 4 , wherein the array of non-volatile memory cells form an analog neural memory.
7. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a control gate terminal, a source line terminal and an erase gate terminal, the method comprising:
ramping up a voltage on control gate terminals of the word of non-volatile memory cells to a first intermediate voltage during a first time period;
ramping up a voltage on the source line terminal of the word of non-volatile memory cells to a second intermediate voltage during a second time period after the first time period;
ramping up a voltage on the erase gate line terminal of the word of non-volatile memory cells and further ramping up the voltage on the source line terminals of the word of non-volatile memory cells and further ramping up the voltage on the control gate terminals of the word of non-volatile memory cells to a third intermediate voltage during a third time period after the second time period; and
ramping up the voltage on control gate terminals of the word of non-volatile memory cells during a fourth time period after the third time period.
8. The method of claim 7 , further comprising:
ramping down the voltage on control gate terminals of the word of non-volatile memory cells to the third intermediate voltage during a fifth time period after the fourth time period;
ramping down the voltage on the source line terminals of the word of non-volatile memory cells to the second intermediate voltage during a sixth time period after the fifth time period;
ramping down the voltage on control gate terminals of the word of non-volatile memory cells to the first intermediate voltage during a seventh time period after the sixth time period;
ramping down the voltage on erase gate terminals of the word of non-volatile memory cells during an eighth time period after the seventh time period;
ramping down the voltage on source line terminals of the word of non-volatile memory cells during the eighth time period after the seventh time period; and
ramping down the voltage on the control gate terminals of the word of non-volatile memory cells during a ninth time period after the eighth time period.
9. The method of claim 7 , wherein the array of non-volatile memory cells form an analog neural memory.
10. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a control gate terminal, a source line terminal and an erase gate terminal, the method comprising:
ramping up a voltage on the source line terminal of the word of non-volatile memory cells during a first time period; and
ramping up a voltage on the erase gate line terminal of the word of non-volatile memory cells and ramping up a voltage on control gate terminals of the word of non-volatile memory cells during a second time period after the first time period.
11. The method of claim 10 , further comprising:
ramping down the voltage on the erase gate line terminals of the word of non-volatile memory cells and ramping down the voltage on the control gate terminals of the word of non-volatile memory cells during a third time period after the second time period; and
ramping down the voltage on the source line terminals of the word of non-volatile memory cells during a fourth time period after the third time period.
12. The method of claim 10 , wherein the array of non-volatile memory cells form an analog neural memory.
13. A method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a control gate terminal, a source line terminal and an erase gate terminal, the method comprising:
ramping up a voltage on control gate terminals of the word of non-volatile memory cells during a time period with multiple ramp steps.
14. The method of claim 13 , further comprising:
ramping up a voltage on the source line terminal of the word of non-volatile memory cells.
15. The method of claim 13 , further comprising:
ramping up a voltage on the erase gate line terminal of the word of non-volatile memory cells.
16. The method of claim 13 , wherein the array of non-volatile memory cells form an analog neural memory.