Rate matching methods for LDPC codes

1. A method of producing a set of coded bits from a set of information bits for transmission between a first node and a second node in a wireless communications system, the method comprising:

generating a codeword vector by encoding the set of information bits with a low- density parity-check code that is specified through a parity check matrix;

puncturing a multiple of Z of the information bits from the codeword vector before writing the codeword vector into a circular buffer, where Z is a lifting factor of the parity check matrix and where the punctured multiple of Z bits have a higher column weight than non-punctured bits; and

performing circular buffer-based rate matching on the punctured codeword vector to produce the coded bits for transmission.

2. The method of claim 1 , wherein the multiple of Z of the information bits that are punctured precedes other information bits that are not punctured.

3. The method of claim 1 , wherein a plurality of redundancy versions are defined over the circular buffer such that coded bits for a retransmission are read from the circular buffer according to a corresponding redundancy version defined for the retransmission.

4. The method of claim 1 , wherein performing circular buffer-based rate matching to produce the coded bits for transmission comprises:

if a number of bits of the transmission vector is larger than the total number of bits in the circular buffer, repeating one or more bits in the circular buffer by wrapping around.

5. The method of claim 1 , wherein generating the codeword vector by encoding the set of information bits comprises:

attaching dummy bits to the set of information bits, the dummy bits comprising bits of known value, to produce an information vector; and

encoding the information vector.

6. The method of claim 5 , comprising puncturing the attached dummy bits.

7. The method of claim 6 , wherein puncturing the attached dummy bits comprises skipping the attached dummy bits when performing circular buffer-based rate matching.

8. The method of claim 1 , wherein performing circular buffer-based rate matching comprises implementing a channel interleaver on the punctured codeword vector.

9. A first node for producing a set of coded bits from a set of information bits for transmission to a second node in a wireless communications system, the first node comprising:

processing circuitry, the processing circuitry configured to:

generate a codeword vector by encoding the set of information bits with a low-density parity-check code that is specified through a parity check matrix; and

puncture a multiple of Z of the information bits from the codeword vector before writing the codeword vector into a circular buffer, where Z is a lifting factor of the parity check matrix and where the punctured multiple of Z bits have a higher column weight than non-punctured bits; and

perform circular buffer-based rate matching on the punctured codeword vector to produce the coded bits for transmission.

10. The first node of claim 9 , wherein the multiple of Z of the information bits that are punctured precedes other information bits that are not punctured.

11. The first node of claim 9 , wherein a plurality of redundancy versions are defined over the circular buffer such that coded bits for a retransmission are read from the circular buffer according to a corresponding redundancy version defined for the retransmission.

12. The first node of claim 9 , wherein the processing circuitry configured to perform circular buffer-based rate matching to produce the coded bits for transmission comprises processing circuitry configured to:

if a number of bits of the transmission vector is larger than the total number of bits in the circular buffer, repeat one or more bits in the circular buffer by wrapping around.

13. The first node of claim 9 , wherein the processing circuitry configured to generate the codeword vector by encoding the set of information bits comprises processing circuitry configured to:

attach dummy bits to the set of information bits, the dummy bits comprising bits of known value, to produce an information vector; and

encode the information vector.

14. The first node of claim 9 , wherein the processing circuitry is further configured to puncture the attached dummy bits.

15. The first node of claim 14 , wherein the processing circuitry configured to puncture the attached dummy bits comprises processing circuitry configured to skip the attached dummy bits when reading the punctured codeword vector from the circular buffer.

16. The first node of claim 9 , wherein the processing circuitry is configured to implement a channel interleaver on the punctured codeword vector as part of the circular buffer-based rate matching.