IP Library › Granted Patent US 12,651,554
Granted Patent B2
US 12,651,554 · App. 18/103,710 · Granted Jun 9, 2026

Display panel and display device

Inventor: Yong Yuan (Xiamen, CN)
Assignee: Xiamen Tianma Display Technology Co., Ltd.
G09G3/32G09G2310/061G09G2320/0233
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Quick Facts
Patent No.
US 12,651,554
App. No.
18/103,710
Granted
Jun 9, 2026
Kind
B2
Abstract

Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module, a data write module, a compensation module and a reset module. The drive module includes a drive transistor; the data write module is connected to a first electrode of the drive transistor; the compensation module is connected between a gate of the drive transistor and a second electrode of the drive transistor; and the reset module is connected to the gate of the drive transistor or the second electrode of the drive transistor. The working process of the pixel circuit includes a first bias adjustment stage, and the first bias adjustment stage includes a first stage; and in the first stage, the data write module and the reset module are turned off, and the compensation module is turned on.

Claims (75)

1 . A display panel, comprising:

a pixel circuit and a light-emitting element, wherein

the pixel circuit comprises a drive module, a data write module, a compensation module and a reset module, wherein

the drive module comprises a drive transistor;

the data write module is connected to a first electrode of the drive transistor;

the compensation module is connected between a gate of the drive transistor and a second electrode of the drive transistor; and

the reset module is connected to the gate of the drive transistor or the second electrode of the drive transistor;

wherein a working process of the pixel circuit comprises a first bias adjustment stage, and the first bias adjustment stage comprises a first stage; and in the first stage, the data write module and the reset module are turned off, and the compensation module is turned on;

wherein the pixel circuit further comprises a bias adjustment module, and the bias adjustment module is connected to the first electrode of the drive transistor or the second electrode of the drive transistor; and in the first stage, the bias adjustment module is turned off; and

wherein the first bias adjustment stage further comprises a third stage, the first stage and the third stage are performed sequentially; and in the third stage, the bias adjustment module is turned on, and the compensation module is turned off.

2 . The display panel according to claim 1 , wherein,

a time duration of the first stage is longer than a time duration of the third stage.

3 . The display panel according to claim 1 , wherein,

the first stage starts at an end of the third stage; or

the third stage starts at an end of the first stage.

4 . The display panel according to claim 1 , wherein,

a third interval stage is located between an end of the first stage and a start of the third stage.

5 . The display panel according to claim 4 , wherein the third interval stage satisfies at least one of:

a time duration of the third interval stage is shorter than a time duration of the first stage; or

a time duration of the third interval stage is shorter than a time duration of the third stage.

6 . The display panel according to claim 1 , wherein,

the first bias adjustment stage further comprises a second stage, and the first stage, the third stage and the second stage are performed sequentially, wherein

in the second stage, the compensation module is turned off, and the reset module is turned on;

a third interval stage is located between an end of the first stage and a start of the third stage, and a fourth interval stage is located between an end of the third stage and a start of the second stage, wherein

a time duration of the third interval stage is t 3 , a time duration of the fourth interval stage is t 4 , and t 3 ≠t 4 .

7 . The display panel according to claim 6 , wherein t 3 <t 4 .

8 . The display panel according to claim 1 , wherein,

the first bias adjustment stage further comprises a second stage;

in the second stage, the compensation module is turned off, and the reset module is turned on;

the second stage at least partially overlaps the third stage.

9 . The display panel according to claim 8 , wherein the second stage satisfies at least one of:

a start time of the second stage is the same as or earlier than a start time of the third stage; or

an end time of the second stage is the same as or later than an end time of the third stage.

10 . The display panel according to claim 8 , wherein,

a start time of the second stage is earlier than a start time of the third stage; and

an end time of the second stage is earlier than an end time of the third stage.

11 . The display panel according to claim 1 , wherein,

the first bias adjustment stage further comprises a second stage, and the first stage and the second stage are performed sequentially; and

in the second stage, the compensation module is turned off, and the reset module is turned on.

12 . The display panel according to claim 11 , wherein,

a time duration of the first stage is longer than a time duration of the second stage.

13 . The display panel according to claim 11 , wherein,

the second stage starts at an end of the first stage.

14 . The display panel according to claim 11 , wherein,

a first interval stage is located between an end of the first stage and a start of the second stage.

15 . A display panel, comprising:

a pixel circuit and a light-emitting element, wherein

the pixel circuit comprises a drive module, a data write module, a compensation module and a reset module, wherein

the drive module comprises a drive transistor;

the data write module is connected to a first electrode of the drive transistor;

the compensation module is connected between a gate of the drive transistor and a second electrode of the drive transistor; and

the reset module is connected to the gate of the drive transistor or the second electrode of the drive transistor;

wherein a working process of the pixel circuit comprises a first bias adjustment stage, and the first bias adjustment stage comprises a first stage; and in the first stage, the data write module and the reset module are turned off, and the compensation module is turned on;

the first bias adjustment stage further comprises a second stage, and the first stage and the second stage are performed sequentially; and

in the second stage, the compensation module is turned off, and the reset module is turned on.

16 . The display panel according to claim 15 , wherein,

a time duration of the first stage is longer than a time duration of the second stage.

17 . The display panel according to claim 15 , wherein,

the second stage starts at an end of the first stage.

18 . The display panel according to claim 15 , wherein,

a first interval stage is located between an end of the first stage and a start of the second stage.

19 . The display panel according to claim 18 , wherein the first interval stage satisfies at least one of:

a time duration of the first interval stage is shorter than a time duration of the first stage; or

a time duration of the first interval stage is shorter than a time duration of the second stage.

20 . A display device, comprising a display panel,

wherein the display panel comprises:

a pixel circuit and a light-emitting element, wherein

the pixel circuit comprises a drive module, a data write module, a compensation module and a reset module, wherein

the drive module comprises a drive transistor;

the data write module is connected to a first electrode of the drive transistor;

the compensation module is connected between a gate of the drive transistor and a second electrode of the drive transistor; and

the reset module is connected to the gate of the drive transistor or the second electrode of the drive transistor;

wherein a working process of the pixel circuit comprises a first bias adjustment stage, and the first bias adjustment stage comprises a first stage; and in the first stage, the data write module and the reset module are turned off, and the compensation module is turned on;

wherein the pixel circuit further comprises a bias adjustment module, and the bias adjustment module is connected to the first electrode of the drive transistor or the second electrode of the drive transistor; and in the first stage, the bias adjustment module is turned off; and

wherein the first bias adjustment stage further comprises a third stage, the first stage and the third stage are performed sequentially; and in the third stage, the bias adjustment module is turned on, and the compensation module is turned off.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2023
From: YUAN, YONG
To: XIAMEN TIANMA DISPLAY TECHNOLOGY CO., LTD.
Reel/Frame 062583/0587 →
Priority Claims (1)
CN 202211028570.2 · Aug 25, 2022 · national
Continuity (1)
Related Publication 20230178008A1 · Jun 8, 2023
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