Display panel comprising a pixel circuit and display device comprising a pixel circuit

1. A display panel, comprising:

a first display region and a second display region; and

a pixel circuit comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region;

wherein the pixel circuit comprises a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor; wherein

a control terminal of the first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of the first presetting module in the second pixel circuit is configured to receive a second control signal; and

in at least one stage in a working process of the display panel, a pulse variation frequency of the first control signal is F 1 , and a pulse variation frequency of the second control signal is F 2 , wherein F 1 ≠F 2 ; and

wherein the pixel circuit further comprises a second presetting module; and

a control terminal of a second presetting module in the first pixel circuit is configured to receive a fourth control signal, and a control terminal of a second presetting module in the second pixel circuit is configured to receive a fifth control signal; wherein

in at least one stage in the working process of the display panel, a pulse variation frequency of the fourth control signal is F 4 , and a pulse variation frequency of the fifth control signal is F 5 ; and

|F 1 −F 2 |>|F 4 −F 5 |≥0.

2. The display panel according to claim 1 , wherein

the first presetting module is a data write module connected to a first electrode of the drive transistor and configured to provide a data signal for the drive transistor; or

the first presetting module is a compensation module connected between a gate of the drive transistor and a second electrode of the drive transistor and configured to compensate for a threshold voltage deviation of the drive transistor; or

the first presetting module is a reset module connected to a gate of the drive transistor or a second electrode of the drive transistor and configured to provide a reset signal for the drive transistor; or

the first presetting module is a bias adjustment module connected to a first electrode of the drive transistor or a second electrode of the drive transistor and configured to provide a bias adjustment signal for the drive transistor.

3. The display panel according to claim 2 , wherein

in at least one stage in the working process of the display panel, a data refresh rate of the first pixel circuit is higher than a data refresh rate of the second pixel circuit; wherein

in response to the first presetting module being the data write module, the compensation module, or the reset module, F 1 >F 2 ; or

in response to the first presetting module being the bias adjustment module, F 1 <F 2 , or F 1 >F 2 .

4. The display panel according to claim 1 , wherein (F 1 −F 2 )×(F 4 −F 5 ) ≥0.

5. The display panel according to claim 1 , wherein

the second presetting module is a light emission control module, wherein the light emission control module is connected between a first power signal terminal and the drive transistor or between the drive transistor and the light-emitting element and is configured to selectively allow the light-emitting element to enter a light emission stage; or

the second presetting module is an initialization module, and the initialization module is connected between an initialization signal terminal and the light-emitting element and is configured to provide an initialization signal for the light-emitting element; or

the second presetting module is a bias adjustment module connected to a first electrode of the drive transistor or a second electrode of the drive transistor and configured to provide a bias adjustment signal for the drive transistor.

6. The display panel according to claim 1 , wherein

the first presetting module in the first pixel circuit comprises a first transistor, and the first presetting module in the second pixel circuit comprises a second transistor, wherein an active layer of the first transistor and an active layer of the second transistor each comprise an oxide semiconductor; and

the second presetting module in the first pixel circuit comprises a third transistor, and the second presetting module in the second pixel circuit comprises a fourth transistor, wherein an active layer of the third transistor and an active layer of the fourth transistor each comprise silicon.

7. The display panel according to claim 1 , wherein

the pixel circuit comprises a bias adjustment module connected to a first electrode of the drive transistor or a second electrode of the drive transistor and configured to provide a bias adjustment signal for the drive transistor; and

a bias adjustment module in the first pixel circuit is configured to receive a first bias adjustment signal Vb 1 , and a bias adjustment module in the second pixel circuit is configured to receive a second bias adjustment signal Vb 2 .

8. The display panel according to claim 7 , wherein Vb 1 ≠Vb 2 , and (F 1 −F 2 )×(Vb 1 −Vb 2 )<0 or (F 1 −F 2 )×(Vb 1 −Vb 2 )>0.

9. The display panel according to claim 7 , wherein F 1 >F 2 , and |F 1 /F 2 |>|Vb 1 /Vb 2 |.

10. The display panel according to claim 7 , comprising:

a bias adjustment signal bus providing the first bias adjustment signal Vb 1 for the first pixel circuit through a bias adjustment signal line and providing the second bias adjustment signal Vb 2 for the second pixel circuit through a bias adjustment signal line; wherein

when the bias adjustment module in the first pixel circuit is turned on, the bias adjustment module in the second pixel circuit is turned off, and a signal on the bias adjustment signal bus is the first bias adjustment signal Vb 1 ; and

when the bias adjustment module in the first pixel circuit is turned off, the bias adjustment module in the second pixel circuit is turned on, and a signal on the bias adjustment signal bus is the second bias adjustment signal Vb 2 .

11. The display panel according to claim 7 , comprising:

a first bias adjustment signal bus and a second bias adjustment signal bus; wherein

the first bias adjustment signal bus provides the first bias adjustment signal Vb 1 for the first display region through a first bias adjustment signal line; and

the second bias adjustment signal bus provides the second bias adjustment signal Vb 2 for the second display region through a second bias adjustment signal line.

12. The display panel according to claim 1 , comprising:

an initialization module, wherein the initialization module is connected between an initialization signal terminal and the light-emitting element and is configured to provide an initialization signal for the light-emitting element; and

an initialization module in the first pixel circuit is configured to provide a first initialization signal Vi 1 for the light-emitting element in the first display region, and an initialization module in the second pixel circuit is configured to provide a second initialization signal Vi 2 for the light-emitting element in the second display region.

13. The display panel according to claim 12 , wherein Vi 1 ≠Vi 2 , and (F 1 −F 2 )×(|Vi 1 |−|Vi 2 |) <0 or (F 1 −F 2 )×(|Vi 1 |−|Vi 2 |)>0.

14. The display panel according to claim 12 , wherein F 1 >F 2 , and |F 1 /F 2 |>|Vi 1 /Vi 2 |.

15. The display panel according to claim 12 , comprising:

an initialization signal bus providing the first initialization signal Vi 1 for the first pixel circuit through an initialization signal line and providing the second initialization signal Vi 2 for the second pixel circuit through an initialization signal line; wherein

when the initialization module in the first pixel circuit is turned on, the initialization module in the second pixel circuit is turned off, and a signal on the initialization signal line is the first initialization signal Vi 1 ; and

when the initialization module in the first pixel circuit is turned off, the initialization module in the second pixel circuit is turned on, and a signal on the initialization signal line is the second initialization signal Vi 2 .

16. The display panel according to claim 12 , comprising:

a first initialization signal bus and a second initialization signal bus; wherein

the first initialization signal bus provides the first initialization signal Vi 1 for the first display region through a first initialization signal line; and

the second initialization signal bus provides the second initialization signal Vi 2 for the second display region through a second initialization signal line.

17. The display panel according to claim 1 , wherein

in at least one stage of the working process of the display panel, the light-emitting element in the first display region works in a first brightness mode, the light-emitting element in the second display region works in a second brightness mode, brightness in the first brightness mode is L 1 , and brightness in the second brightness mode is L 2 , wherein L 1 ≠L 2 .

18. A display device, comprising a display panel,

wherein the display panel comprises:

a first display region and a second display region; and

a pixel circuit comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region;

wherein the pixel circuit comprises a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor; wherein

a control terminal of the first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of the first presetting module in the second pixel circuit is configured to receive a second control signal; and

in at least one stage in a working process of the display panel, a pulse variation frequency of the first control signal is F 1 , and a pulse variation frequency of the second control signal is F 2 , wherein F 1 ≠F 2 ; and

wherein the pixel circuit further comprises a second presetting module; and

a control terminal of a second presetting module in the first pixel circuit is configured to receive a fourth control signal, and a control terminal of a second presetting module in the second pixel circuit is configured to receive a fifth control signal; wherein

in at least one stage in the working process of the display panel, a pulse variation frequency of the fourth control signal is F 4 , and a pulse variation frequency of the fifth control signal is F 5 ; and

|F 1 -F 2 |>|F 4 −F 5 |≥0.