SRAM cell with write enhance pass gate transistors
Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.
1 . A SRAM (static random access memory) bit cell, comprising:
a first inverter having a data storage node;
a second inverter cross-coupled to the first inverter and having a data bar storage node;
a first pass gate transistor coupled between the data storage node and a bit line conductor, wherein the first pass gate transistor includes a first gate terminal connected to a first word line conductor;
a second pass gate transistor coupled between the data bar storage node and a bit line bar conductor, wherein the second gate transistor includes a second gate terminal connected to the first word line conductor;
a third pass gate transistor coupled between the data storage node and the bit line conductor, wherein the third pass gate transistor includes a third gate terminal connected to a second word line conductor; and
a fourth pass gate transistor coupled between the data storage bar node and the bit line bar conductor, wherein the fourth pass gate transistor includes a fourth gate terminal connected to the second word line conductor,
wherein drains of the first and third pass gate transistors are coupled to the bit line bar conductor, and sources of the second and fourth pass gate transistors are coupled to the bit line bar conductor.
2 . The SRAM bit cell of claim 1 , wherein the first pass gate transistor and the second pass gate transistor are transistors of a first type, and the third pass gate transistors and the fourth pass gate transistors are transistors of a second type.
3 . The SRAM bit cell of claim 2 , wherein the first pass gate transistor and the second pass gate transistor are NMOS field effect transistors, and the third pass gate transistors and the fourth pass gate transistors are PMOS field effect transistors.
4 . The SRAM bit cell of claim 2 , wherein the first pass gate transistor and the second pass gate transistor are PMOS field effect transistors, and the third pass gate transistors and the fourth pass gate transistors are NMOS field effect transistors.
5 . The SRAM bit cell of claim 2 , wherein the first pass gate transistor and the third pass gate transistor are vertically stacked, and the second pass gate transistor and the fourth pass gate transistor are vertically stacked.
6 . The SRAM bit cell of claim 5 , wherein
the first inverter comprises:
a first pull up transistor; and
a first pull down transistor, wherein the first pull up transistor and the first pull down transistor are vertically stacked; and
the second inverter comprises:
a second pull up transistor; and
a second pull down transistor, wherein the second pull up transistor and the second pull down transistor are vertically stacked.
7 . The SRAM bit cell of claim 6 , wherein the first and second gate terminals are disposed on a front side to connect with a front side interconnect structure, and the third and fourth gate terminals are disposed on a back side to connect with a back side interconnect structure.
8 . The SRAM bit cell of claim 1 , wherein the first pass gate transistor and the third pass gate transistor have a same channel width.
9 . A SRAM bit cell, comprising:
a first inverter having a data storage node, wherein the first inverter comprises:
a first pull-up transistor; and
a first pull-down transistor;
a second inverter cross-coupled to the first inverter and having a data bar storage node, wherein the second inverter comprises:
a second pull-up transistor; and
a second pull-down transistor;
a first pass gate transistor coupled between the data storage node and a bit line conductor, wherein the first pass gate transistor includes a first gate terminal connected to a first word line conductor;
a second pass gate transistor coupled between the data bar storage node and a bit line bar conductor, wherein the second gate transistor includes a second gate terminal connected to the first word line conductor;
a third pass gate transistor coupled between the data storage node and the bit line conductor, wherein the third pass gate transistor includes a third gate terminal connected to a second word line conductor; and
a fourth pass gate transistor coupled between the data storage bar node and the bit line bar conductor, wherein the fourth pass gate transistor includes a fourth gate terminal connected to the second word line conductor,
wherein the first pass gate transistor and the third pass gate transistor are complementary transistors;
wherein drains of the first and third pass gate transistors are coupled to the bit line bar conductor, and sources of the second and fourth pass gate transistors are coupled to the bit line bar conductor.
10 . The SRAM bit cell of claim 9 , wherein the first pull-up transistor and second pull-up transistor are formed in a p-type transistor level, and the first pull-down transistor and the second pull-down transistor are formed in a n-type transistor level.
11 . The SRAM bit cell of claim 10 , wherein the first pull up transistor and the first pull down transistor are vertically stacked, and the second pull up transistor and the second pull down transistor are vertically stacked.
12 . The SRAM bit cell of claim 11 , wherein the first pass gate transistor and the third pass gate transistor are complementary transistors.
13 . The SRAM bit cell of claim 12 , wherein the first pass gate transistor is formed in the p-type transistor level and the third pass gate transistor is formed in the n-type transistor level.
14 . A SRAM bit cell, comprising:
a first inverter having a data storage node;
a second inverter cross-coupled to the first inverter and having a data bar storage node;
a first pass gate transistor coupled between the data storage node and a bit line conductor, wherein the first pass gate transistor includes a first gate terminal connected to a first word line conductor;
a second pass gate transistor coupled between the data bar storage node and a bit line bar conductor, wherein the second gate transistor includes a second gate terminal connected to the first word line conductor;
a third pass gate transistor coupled between the data storage node and the bit line conductor, wherein the third pass gate transistor includes a third gate terminal connected to a second word line conductor; and
a fourth pass gate transistor coupled between the data storage bar node and the bit line bar conductor, wherein the fourth pass gate transistor includes a fourth gate terminal connected to the second word line conductor,
wherein the first pass gate transistor and the second pass gate transistor are transistors of a first type, and the third pass gate transistors and the fourth pass gate transistors are transistors of a second type,
wherein drains of the first and third pass gate transistors are coupled to the bit line bar conductor, and sources of the second and fourth pass gate transistors are coupled to the bit line bar conductor.
15 . The SRAM bit cell of claim 14 , wherein the first pass gate transistor and the second pass gate transistor are NMOS field effect transistors, and the third pass gate transistors and the fourth pass gate transistors are PMOS field effect transistors.
16 . The SRAM bit cell of claim 14 , wherein the first pass gate transistor and the second pass gate transistor are PMOS field effect transistors, and the third pass gate transistors and the fourth pass gate transistors are NMOS field effect transistors.
17 . The SRAM bit cell of claim 14 , wherein the first pass gate transistor and the third pass gate transistor have a same channel width.
18 . The SRAM bit cell of claim 17 , wherein
the first inverter comprises:
a first pull up transistor; and
a first pull down transistor, wherein the first pull up transistor and the first pull down transistor are vertically stacked; and
the second inverter comprises:
a second pull up transistor; and
a second pull down transistor, wherein the second pull up transistor and the second pull down transistor are vertically stacked.
19 . The SRAM bit cell of claim 18 , wherein the first and second gate terminals are disposed on a front side to connect with a front side interconnect structure, and the third and fourth gate terminals are disposed on a back side to connect with a back side interconnect structure.
20 . The SRAM bit cell of claim 14 , wherein the first pass gate transistor and the third pass gate transistor are complementary transistors.