Selective decoding for super chip-kill recovery and method of operating such memory system

1. A memory system comprising:

a memory block; and

a memory controller in communication with the memory block, wherein the memory controller is configured to:

decode codewords from the memory block,

identify failed codewords from the decoded codewords,

sort failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and

perform a soft uncorrectable page error (super) chip kill (SCK) operation by determining, from successfully decoded pages in a stripe of the failed sector, information on which bits in the failed codewords are in error and using this information to generate a log likelihood ratio (LLR) for decoding one of the failed codewords in the first set which has the lowest bit error rate in the failed sector to produce a recovered codeword.

2. The memory system of claim 1 , wherein the first set of the failed codewords has lower estimated raw bit error rates RBERs than the second set of the failed codewords.

3. The memory system of claim 2 , wherein the memory controller is configured to perform the SCK operation on the failed sector in order of the best case failed codeword to the worst case failed codeword.

4. The memory system of claim 1 , wherein

the first set includes a best case failed codeword having the lowest estimated RBER of all estimated RBERs in the failed sector, and

the second set includes a worst case failed codeword having the highest estimated RBER of all the estimated RBERs.

5. The memory system of claim 1 , wherein the memory controller is configured to utilize failed decoding attempt observables to estimate a probability of a failed codeword being successfully decoded.

6. The memory system of claim 5 , wherein the memory controller is configured to utilize a failure margin estimator to provide relative values for the failed codewords to be properly decoded based on the failed decoding attempt observables.

7. The memory system of claim 6 , wherein the failed decoding attempt observables comprise at least one or more of an initial checksum of a failed codeword prior to decoding, a number of decoding iterations for the failed codeword prior to a threshold number of iterations, and an end checksum of the failed codeword after the iterations.

8. The memory system of claim 1 , wherein the memory controller is configured to terminate the SCK operation on one of the failed codewords when there are more than a preset number of decoding failures.

9. The memory system of claim 8 , wherein the termination of the SCK operation on one of the failed codewords reduces an overall latency of the SCK operation in decoding the memory block.

10. The memory system of claim 1 , wherein, in the SCK operation, the recovered codeword reduces a number of failed codewords and increases a probability of another failed codeword being recovered.

11. A method for selective decoding a memory block using soft uncorrectable page error (super) chip kill (SCK), comprising:

decoding codewords from the memory block;

identifying failed codewords from the decoded codewords;

sorting failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and

performing a SCK operation by determining, from successfully decoded pages in a stripe of the failed sector, information on which bits in the failed codewords are in error and using this information to generate a log likelihood ratio (LLR) for decoding one of the failed codewords in the first set which has the lowest bit error rate in the failed sector to produce a recovered codeword.

12. The method of claim 11 , wherein the first set of the failed codewords has lower estimated raw bit error rates RBERs than the second set of the failed codewords.

13. The method of claim 12 , further comprising performing the SCK operation on the failed sector in order of the best case failed codeword to the worst case failed codeword.

14. The method of claim 11 , wherein

the first set includes a best case failed codeword having the lowest estimated RBER of all the estimated RBERs in the failed sector, and

the second set includes a worst case failed codeword having the highest estimated RBER of all the estimated RBERs.

15. The method of claim 11 , wherein the estimating comprises:

using failed decoding attempt observables to estimate a probability of a failed codeword being successfully decoded.

16. The method of claim 15 , further comprising using a failure margin estimator to provide relative values for the failed codewords to be properly decoded based on the failed decoding attempt observables.

17. The method of claim 16 , wherein the failed decoding attempt observables comprise at least one or more of an initial checksum of a failed codeword prior to decoding, a number of decoding iterations for the failed codeword prior to a threshold number of iterations, and an end checksum of the failed codeword after the iterations.

18. The method of claim 11 , wherein the SCK operation on one of the failed codewords is terminated when there are more than a preset number of decoding failures.

19. The method of claim 18 , wherein the termination of the SCK operation on one of the failed codewords reduces an overall latency of the SCK operation in decoding the memory block.

20. The method of claim 11 , wherein, in the SCK operation, the recovered codeword reduces a number of failed codewords and increases a probability of another failed codeword being recovered.