SEMICONDUCTOR PACKAGE HAVING A THICK LOGIC DIE
A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.
1 . A semiconductor package, comprising:
a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween;
a logic die mounted on a top surface of the bottom substrate, wherein the logic die has a thickness of 125-350 micrometers;
a plurality of copper cored solder balls disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate; and
a sealing resin filling in the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.
2 . The semiconductor package according to claim 1 , wherein the logic die is mounted on the top surface of the bottom substrate in a flip-chip fashion.
3 . The semiconductor package according to claim 2 , wherein the logic die comprises an active front side and a passive rear side, and wherein, a plurality of input/output (I/O) pads is provided on the active front side.
4 . The semiconductor package according to claim 3 , wherein the logic die is electrically connected to the bottom substrate through a plurality of conductive elements formed on the plurality of I/O pads, respectively.
5 . The semiconductor package according to claim 4 , wherein underfill resin is disposed in a space between the logic die and the top surface of the bottom substrate, and wherein the conductive elements are surrounded by the underfill resin.
6 . The semiconductor package according to claim 1 , wherein the bottom substrate and the top substrate are printed wiring boards or package substrates.
7 . The semiconductor package according to claim 1 , wherein the gap has a gap height ranging between 160-450 micrometers.
8 . The semiconductor package according to claim 1 , wherein an aspect ratio of the plurality of copper cored solder balls ranges between 1.1-2.0.
9 . The semiconductor package according to claim 1 , wherein a ball pitch of the plurality of copper cored solder balls is 0.2-0.3 mm.
10 . The semiconductor package according to claim 1 , wherein each of the plurality of copper cored solder balls comprises a copper core coated with a solder layer.
11 . The semiconductor package according to claim 1 , wherein external connection terminals are disposed on a bottom surface of the bottom substrate.
12 . A package on package, comprising:
a semiconductor package according to claim 1 ; and
a memory package mounted on the semiconductor package.
13 . The package on package according to claim 12 , wherein the memory package comprises a LPDDR DRAM package.