Apparatuses and methods for compute enabled cache

1. An apparatus, comprising:

a memory device comprising a memory array and sensing circuitry comprising a plurality of sense amplifiers and an array of processor in memory (PIM) blocks to perform logical operations;

a host coupled to the memory device and comprising a cache controller, the cache controller configured to:

create a block select as metadata to a cache line to control alignment of the cache line to a column of the memory array based on a configuration of the array of PIM blocks for processing.

2. The apparatus of claim 1 , wherein the host comprises a processing resource coupled to a last level cache (LLC) via through silicon vias (TSVs) and wherein the cache line is moved from the LLCs to the memory device.

3. The apparatus of claim 2 , wherein the block select corresponds to a width of an interface coupling the host to the memory device.

4. The apparatus of claim 1 , wherein the memory device is a last level cache (LLC) memory.

5. The apparatus of claim 4 , wherein the plurality of sense amplifiers is configured to access and to operate on cached data in the LLC memory without moving the cached data to a higher level in the memory.

6. The apparatus of claim 1 , wherein a controller of the memory device is configured to:

change the block select and a subrow select;

relocate the cached data transparently to a host processor of the host; and

wherein the block select and the subrow select are not part of an address space of the host processor.

7. The apparatus of claim 6 , wherein the cache controller is configured to store a copy of the block select and the subrow select with the host processor.

8. The apparatus of claim 1 , wherein the memory device is configured to:

use the block select to control alignment of cached data in the memory array; and

use a subrow select to control resource allocation in the memory array.

9. An apparatus, comprising:

a host;

a memory device coupled to the host comprising a memory array and an array of processor in memory (PIM) blocks, and configured to:

receive a cache line having block select metadata from the host processor; and

operate on the block select metadata to control alignment of the cache line to a column of the memory array based on a configuration of the array of PIM blocks for processing.

10. The apparatus of claim 9 , wherein the host further includes a cache controller to create the block select metadata and insert to the cache line.

11. The apparatus of claim 9 , wherein the block select metadata a is stored internal to the memory device and are transparent to an address space of a processing resource of the host.

12. The apparatus of claim 9 , wherein the memory device is configured to:

store the cache blocks in the array; and

retrieve a cache line to perform logical operations with the array of PIM blocks.

13. A system for operating a cache memory, comprising:

a host processor; and

a memory coupled to the host processor via through silicon vias (TSVs), comprising a memory array and an array of processor in memory (PIM) blocks, and configured to:

receive a cache line having block select metadata; and

control alignment, utilizing the block select metadata, of the cache line to a column of the memory array based on a configuration of the array of PIM blocks for processing.

14. The system of claim 13 , wherein the memory is a three dimensional (3D) integrated memory.

15. The system of claim 14 , wherein memory banks of the memory have independent TSV paths coupling the memory banks to the host processor.

16. The system of claim 14 , further comprising a cache controller configured to control the TSV paths.

17. The system of claim 14 , wherein the host processor is further configured to move the cache line having the block select metadata from a static random access memory (SRAM) of the host processor to the memory.

18. The system of claim 13 , wherein the column includes a column of memory cells of the memory array that comprise a cache block.

19. The system of claim 18 , wherein the cache block is an addressable area in memory that is used to perform an operation using the array of PIM blocks.

20. The system of claim 19 , wherein the cache line has a bit length that is smaller than a bit length of the cache block.