Method and memory used for reducing program disturbance by adjusting voltage of dummy word line

1. A method for operating a memory, the memory comprising: a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line, wherein the first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines, the method comprising:

applying a first pass voltage to the first dummy word line and applying a second pass voltage to the second dummy word line; and

applying a program voltage to a selected word line, wherein a condition is met:

a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

2. The method of claim 1 , wherein the first voltage difference minus the second voltage difference is more than 3 V and less than 7 V.

3. The method of claim 1 , wherein the first threshold voltage of the first dummy cell corresponding to the first dummy word line is different from the second threshold voltage of the second dummy cell corresponding to the second dummy word line.

4. The method of claim 1 , further comprising:

applying a first dummy program voltage to the first dummy cell corresponding to the first dummy word line and applying a second dummy program voltage to the second dummy cell corresponding to the second dummy word line, wherein the first dummy program voltage is different from the second dummy program voltage.

5. The method of claim 1 , further comprising:

applying a pre-pulse voltage to the first dummy cell corresponding to the first dummy word line and the second dummy cell corresponding to the second dummy word line during a pre-pulse phase.

6. The method of claim 5 , wherein:

the pre-pulse voltage is higher than the first threshold voltage of the first dummy cell corresponding to the first dummy word line and the second threshold voltage of the second dummy cell corresponding to the second dummy word line.

7. The method of claim 1 , wherein:

the first dummy word line is between the first group of word lines and the second dummy word line; and

the second dummy word line is between the first dummy word line and the second group of word lines.

8. The method of claim 1 , wherein applying a first pass voltage to the first dummy word line and applying a second pass voltage to the second dummy word line; and applying a program voltage to a selected word line, are performed in a program phase.

9. The method of claim 1 , wherein the first pass voltage is the same as the second pass voltage, and wherein the first threshold voltage of the first dummy cell corresponding to the first dummy word line is different from the second threshold voltage of the second dummy cell corresponding to the second dummy word line.

10. The method of claim 1 , wherein the first pass voltage is different from the second pass voltage, and the first threshold voltage of the first dummy cell corresponding to the first dummy word line is the same as the second threshold voltage of the second dummy cell corresponding to the second dummy word line.

11. A memory device, comprising:

a memory cell array comprising:

a first group of word lines;

a second group of word lines;

a first dummy word line; and

a second dummy word line, wherein the first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines; and

a driving circuit coupled to the memory cell array and configured to:

apply a first pass voltage to the first dummy word line and apply a second pass voltage to the second dummy word line; and

apply a program voltage to a selected word line, wherein a condition is met:

a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

12. The memory device of claim 11 , wherein the first voltage difference minus the second voltage difference is more than 3 V and less than 7 V.

13. The memory device of claim 11 , wherein the first threshold voltage of the first dummy cell corresponding to the first dummy word line is different from the second threshold voltage of the second dummy cell corresponding to the second dummy word line.

14. The memory device of claim 11 , wherein the driving circuit is configured to:

apply a first dummy program voltage to the first dummy cell corresponding to the first dummy word line; and

apply a second dummy program voltage to the second dummy cell corresponding to the second dummy word line, wherein the first dummy program voltage is different from the second dummy program voltage.

15. The memory device of claim 11 , wherein the driving circuit is configured to: apply a pre-pulse voltage to the first dummy cell corresponding to the first dummy word line and the second dummy cell corresponding to the second dummy word line during a pre-pulse phase.

16. The memory device of claim 11 , wherein:

the first dummy word line is between the first group of word lines and the second dummy word line; and

the second dummy word line is between the first dummy word line and the second group of word lines.

17. The memory device of claim 11 , further comprising:

a joint oxide layer formed between the first group of word lines and the second group of word lines.

18. The memory device of claim 17 , wherein the first dummy word line is between the joint oxide layer and the first group of word lines, and the second dummy word line is between the joint oxide layer and the second group of word lines.

19. The memory device of claim 17 , wherein the first dummy word line is between the joint oxide layer and the first group of word lines, and the second dummy word line is between the first dummy word line and the joint oxide layer.

20. The memory device of claim 17 , further comprising:

a first select line;

a second select line;

a first select gate electrode coupled to the first select line;

a select bit line; and

a second select gate electrode coupled to the second select line, wherein the first group of word lines are between the first select gate electrode and the joint oxide layer.