IP Library Granted Patent US 11,935,854
Granted Patent B2
US 11,935,854 · App. 18/119,266 · Granted Mar 19, 2024

Method for forming bonded semiconductor structure utilizing concave/convex profile design for bonding pads

Inventors: Chung-Sung Chiang (Kaohsiung, TW); Chia-Wei Liu (Tainan, TW); Yu-Ruei Chen (New Taipei, TW); Yu-Hsiang Lin (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L24/06H01L23/488H01L23/53228H01L25/0655
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,935,854
App. No.
18/119,266
Granted
Mar 19, 2024
Kind
B2
Abstract

A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.

Claims (10)

1. A method for forming a bonded semiconductor structure, comprising:

providing a first device wafer and a second device wafer, wherein the first device wafer includes a first bonding layer and a first bonding pad exposed from the first bonding layer, the second device wafer includes a second bonding layer and a second bonding pad exposed from the second bonding layer;

removing a portion of the first bonding pad until exposing a sidewall of the first bonding layer, wherein an angle between the sidewall of the first bonding layer and a top surface of the first bonding pad is larger than 90 degrees;

removing a portion of the second bonding layer to expose a sidewall of the second bonding pad; and

bonding the first device wafer and the second device wafer to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad, wherein the conductive bonding interface and the dielectric bonding interface comprise a step-height.

2. The method for forming a bonded semiconductor structure according to claim 1 , wherein the portion of the first bonding pad is removed by performing a chemical mechanical polishing process.

3. The method for forming a bonded semiconductor structure according to claim 1 , wherein the portion of the second bonding layer is removed by performing a wet etching process.

4. The method for forming a bonded semiconductor structure according to claim 3 , wherein the second bonding layer comprises silicon carbonitride (SiCN), and the wet etching process comprises using phosphoric acid (H 3 PO 4 ).

5. The method for forming a bonded semiconductor structure according to claim 1 , the sidewall of the first bonding layer directly contacts the sidewall of the second bonding pad after bonding the first device wafer and the second device wafer.

6. The method for forming a bonded semiconductor structure according to claim 1 , the sidewall of the first bonding layer and the sidewall of the second bonding pad are spaced apart by an air gap.

Priority Claims (1)
CN 202110776523.5 · Jul 9, 2021 · national
Continuity (2)
Division 17406091 · Aug 19, 2021
Related Publication 20230223366A1 · Jul 13, 2023