IP Library Granted Patent US 12,034,010
Granted Patent B2
US 12,034,010 · App. 18/119,624 · Granted Jul 9, 2024

Active matrix substrate

Inventors: Masahiko Suzuki (Sakai, JP); Tetsuo Kikuchi (Sakai, JP); Hideki Kitagawa (Sakai, JP); Setsuji Nishimiya (Sakai, JP); Kengo Hara (Sakai, JP); Hitoshi Takahata (Sakai, JP); Tohru Daitoh (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
H01L27/124H01L27/1222H01L27/1225H01L27/1237H01L27/127H01L29/7869H01L29/78696
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Quick Facts
Patent No.
US 12,034,010
App. No.
18/119,624
Granted
Jul 9, 2024
Kind
B2
Abstract

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Claims (36)

1. An active matrix substrate includes pixel regions, the active matrix substrate comprising:

a substrate;

a first conductive film supported on a main surface of the substrate;

a lower insulating layer covers the first conductive film;

an oxide semiconductor layer located above the lower insulating layer;

a gate insulating layer on the oxide semiconductor layer;

a second conductive film on the gate insulating layer;

an interlayer insulating layer covers the second conductive film;

a third conductive film located above the interlayer insulating layer;

a lower opening provided in the lower insulating layer;

a first opening provided in the interlayer insulating layer;

oxide semiconductor TFTs provided in association with the pixel regions; wherein

at least one of the oxide semiconductor TFTs includes:

the oxide semiconductor layer including a channel region, and a first region and a second region located on respective sides of the channel region;

a gate electrode made of the second conductive film, and overlapping the channel region of the oxide semiconductor layer; and

a source electrode made of the first conductive film, and electrically connected to the first region via a connection portion;

the connection portion includes a first connection region where a connection electrode made of the third conductive film and the first region are electrically connected, and a second connection region where the connection electrode and the source electrode are electrically connected; and

the second connection region is arranged within the lower opening and the first opening.

2. The active matrix substrate of claim 1 ,

wherein

the first connection region is arranged within the first opening.

3. The active matrix substrate according to claim 1 , wherein the gate insulating layer covers the channel region of the oxide semiconductor layer, and does not cover any portion of the first region of the oxide semiconductor layer and any portion of the second region of the oxide semiconductor layer.

4. The active matrix substrate according to claim 1 , wherein the interlayer insulating layer contacts at least a portion of the first region of the oxide semiconductor layer and at least a portion of the second region of the oxide semiconductor layer.

5. The active matrix substrate according to claim 1 , wherein the oxide semiconductor layer includes at least one metal element selected from In, Ga, and Zn.

6. A display device comprising the active matrix substrate according to claim 1 .

7. An organic EL display device comprising the active matrix substrate according to claim 1 .

8. The active matrix substrate according to claim 1 , further comprising:

a second opening provided in the interlayer insulating layer; wherein

the at least one of the oxide semiconductor TFTs further includes a drain electrode; and

the second region and the drain electrode are electrically connected via the second opening.

9. The active matrix substrate according to claim 8 , wherein the drain electrode is formed of the third conductive film.

10. The active matrix substrate according to claim 1 , further comprising:

a first metal film made of the first conductive film; wherein

the first metal film overlaps the channel region of the oxide semiconductor layer.

11. The active matrix substrate according to claim 10 , wherein a first thickness of a region of the lower insulating layer that overlaps the source electrode is less than a second thickness of a region of the lower insulating layer that overlaps the first metal film.

12. The active matrix substrate according to claim 11 , wherein the first thickness is ½ or less of the second thickness.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2023
From: SUZUKI, MASAHIKO; KIKUCHI, TETSUO; KITAGAWA, HIDEKI; NISHIMIYA, SETSUJI; HARA, KENGO; TAKAHATA, HITOSHI; DAITOH, TOHRU
To: SHARP KABUSHIKI KAISHA
Reel/Frame 062939/0278 →
Continuity (3)
Continuation 17156769 · Jan 25, 2021
Provisional Application 62971249 · Feb 7, 2020
Related Publication 20230215876A1 · Jul 6, 2023