IP Library Granted Patent US 12,016,114
Granted Patent B2
US 12,016,114 · App. 18/119,711 · Granted Jun 18, 2024

Setting the impedance of signal traces of a circuit board using a reference trace

Inventors: Manhtien V. Phan (Morgan Hill, CA); Mau-Lin Chou (Milpitas, CA); Chih-Hao Lee (New Taipei, TW)
Assignee: Super Micro Computer, Inc.
H05K1/0253H05K1/0298H05K2201/093
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Quick Facts
Patent No.
US 12,016,114
App. No.
18/119,711
Granted
Jun 18, 2024
Kind
B2
Abstract

A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.

Claims (13)

1. A circuit board comprising:

a dielectric layer;

a first contact finger and a second contact finger that are on an edge connector of the circuit board, the first and second contact fingers being on a first surface of the dielectric layer and configured to carry a differential signal;

a reference plane that is on a second surface of the dielectric layer; and

a reference trace that is within the dielectric layer, the reference trace being directly under and between the first and second contact fingers, the reference trace being configured to set a differential impedance of the first and second contact fingers,

wherein the reference plane, the reference trace, the first contact finger, and the second contact finger each comprises a metal.

2. The circuit board of claim 1 , wherein the reference plane is between the dielectric layer and another layer of the circuit board.

3. The circuit board of claim 1 , wherein the differential impedance of the first and second contact fingers is set to about 85 ohms.

4. The circuit board of claim 1 , wherein the reference trace has a width that is narrower than a spanning distance between outer side perimeters of the first contact finger and the second contact finger.

5. The circuit board of claim 1 , wherein the reference traces comprises copper.

6. The circuit board of claim 1 , wherein the edge connector includes a notch.

7. The circuit board of claim 1 , wherein the reference trace has a first portion that is in parallel with the first and second contact fingers and a second portion that is perpendicular to the first portion.

8. The circuit board of claim 1 , wherein the first and second contact fingers comprise gold.

Assignments (2)
SECURITY INTEREST Recorded Jan 20, 2026
From: SUPER MICRO COMPUTER, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 074447/0643 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2023
From: PHAN, MANHTIEN V.; CHOU, MAU-LIN; LEE, CHIH-HAO
To: SUPER MICRO COMPUTER, INC.
Reel/Frame 062938/0428 →
Continuity (4)
Division 17480696 · Sep 21, 2021
Division 17070167 · Oct 14, 2020
Continuation 16750686 · Jan 23, 2020
Related Publication 20230217583A1 · Jul 6, 2023