Variable resistance memory device
A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by C a Ge b Sb c Te d A e X f , in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.
1. A variable resistance memory device, comprising:
a first conductive line extending on a substrate in a first horizontal direction;
a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and
a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by C a Ge b Sb c Te d A e X f , in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.
2. The variable resistance memory device as claimed in claim 1 , wherein:
A includes indium (In), and
X includes boron (B), aluminum (Al), gallium (Ga), or thallium (Tl).
3. The variable resistance memory device as claimed in claim 2 , wherein X of the first variable resistance layer includes Al.
4. The variable resistance memory device as claimed in claim 2 , wherein 1≤f≤6.
5. The variable resistance memory device as claimed in claim 4 , wherein 2≤f≤4.
6. The variable resistance memory device as claimed in claim 1 , wherein:
A includes Ga, and
X includes B, Al, In, or Tl.
7. The variable resistance memory device as claimed in claim 1 , wherein:
A includes B, and
X includes Al, Ga, In, or Tl.
8. The variable resistance memory device as claimed in claim 1 , wherein the memory cell further includes an intermediate electrode between the selection element and the variable resistor.
9. The variable resistance memory device as claimed in claim 1 , wherein:
the variable resistor further includes a second variable resistance layer on the first variable resistance layer, and
the second variable resistance layer includes GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, ScSbTe, ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, NdSbS, CGeTe, CGeSe, CGeS, CSbSe, CSbTe, CSbS, CSbSe, CSnSb, CInSe, CInSb, CAsTe, CAlTe, CGaSb, CAlSb, CBiSb, CScSb, CYSb, CCeSb, CDySb, or CNdSb.
10. The variable resistance memory device as claimed in claim 1 , wherein:
the variable resistor further includes a third variable resistance layer on the first variable resistance layer, and
the third variable resistance layer includes CGeSbSe, CAlSbTe, CAlSbSe, CSiSbSe, CSiSbTe, CGeSeTe, CInGeTe, CGeSbTe, CGeAsTe, CSnSeTe, CGeGaSe, CBiSbSe, CGaSeTe, CInGeSb, CGaSbSe, CGaSbTe, CInSbSe, CInSbTe, CSnSbSe, CSnSbTe, CScSbTe, CScSbSe, CScSbS, CYSbTe, CYSbSe, CYSbS, CCeSbTe, CCeSbSe, CCeSbS, CDySbTe, CDySbSe, CDySbS, CNdSbTe, CNdSbSe, CNdSbS, GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn, GeSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe, or NdGeSbS.
11. The variable resistance memory device as claimed in claim 1 , wherein:
the variable resistor further includes a fourth variable resistance layer on the first variable resistance layer, and
the fourth variable resistance layer includes InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeScSbSeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeScSbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSbSeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn, GeSbSeTlZn, GeSbSeTlSn, GeSbSeZnSn, CGeSbTeS, CBiSbTeSe, CAgInSbTe, CGeSbSeTe, CGeSnSbTe, CSiGeSbTe, CSiGeSbSe, CSiGeSeTe, CBiGeSeTe, CBiSiGeSe, CBiSiGeTe, CGeSbTeBi, CGeSbSeBi, CGeSbSeIn, CGeSbSeGa, CGeSbSeAl, CGeSbSeTl, CGeSbSeSn, CGeSbSeZn, CGeSbTeIn, CGeSbTeGa, CGeSbTeAl, CGeSbTeTl, CGeSbTeSn, CGeSbTeZn, CScGeSbTe, CScGeSbSe, CScGeSbS, CYGeSbTe, CYGeSbSe, CYGeSbS, CCeGeSbTe, CCeGeSbSe, CCeGeSbS, CDyGeSbTe, CDyGeSbSe, CDyGeSbS, CNdGeSbTe, CNdGeSbSe, or CNdGeSbS.
12. The variable resistance memory device as claimed in claim 1 , wherein:
the variable resistor is on the first variable resistance layer, and
the variable resistor includes a fifth variable resistance layer having a senary component represented by C h Ge i Sb j Te k A′ m X′ n , in which A′ and X′ are each a group 13 element different from each other, and 1≤h≤18, 13≤i≤26, 15≤j≤30, 35≤k≤55, 0.1≤m≤8, 0.1≤n≤8, and h+i+j+k+m+n=100.
13. The variable resistance memory device as claimed in claim 12 , wherein X of the first variable resistance layer and X′ of the fifth variable resistance layer are elements different from each other.
14. The variable resistance memory device as claimed in claim 12 , wherein:
X of the first variable resistance layer and X′ of the fifth variable resistance layer are the same element, and
f of the first variable resistance layer and n of the fifth variable resistance layer are different from each other.
15. A variable resistance memory device, comprising:
a first conductive line extending on a substrate in a first horizontal direction;
a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and
a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor,
wherein the variable resistor includes:
a first variable resistance layer having a senary component including carbon, A, and X, in which, A and X are each a group 13 element different from each other, and
a second variable resistance layer on the first variable resistance layer, the second variable resistance layer including a ternary component including germanium (Ge), antimony (Sb), and tellurium (Te).
16. The variable resistance memory device as claimed in claim 15 , wherein:
the variable resistor further includes:
a third variable resistance layer on the first variable resistance layer, the third variable resistance layer including a quaternary component including Ge, Sb, and Te; or
a fourth variable resistance layer on the first variable resistance layer, the fourth variable resistance layer including a quinary component including Ge, Sb, and Te, and
the variable resistor has a symmetrical structure centered on the first variable resistance layer.
17. The variable resistance memory device as claimed in claim 16 , wherein:
the variable resistor further includes a fifth variable resistance layer on the first variable resistance layer, the fifth variable resistance layer including a senary component including C, A′, and X′, in which A′ and X′ are each a group 13 element different from each other, and
the variable resistor has a symmetrical structure centered on the first variable resistance layer.
18. The variable resistance memory device as claimed in claim 15 , wherein:
A includes In, and
X includes Al.
19. The variable resistance memory device as claimed in claim 18 , wherein a content of X in the senary component is in a range of about 1 at % to about 6 at %.
20. A variable resistance memory device, comprising:
a first conductive line extending on a substrate in a first horizontal direction;
a second conductive line extending on the first conductive line in a second horizontal direction intersecting with the first horizontal direction;
a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor;
a lower electrode contacting a top surface of the first conductive line; and
an upper electrode contacting a bottom surface of the second conductive line,
wherein the variable resistor includes a first variable resistance layer having a senary component represented by C a Ge b Sb c Te d A e X f , in which A and X are each a group 13 element different from each other and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.