Compute Express Link memory and storage module
An apparatus can include control circuitry, a non-volatile memory device, and a volatile memory device. The control circuitry can be configured to receive a command presented according to a compute express link (CXL) protocol. The control circuitry can be further configured to cause data to be written to the non-volatile memory device or the volatile memory device, or both, in response to receipt of the command while refraining from writing the data to a cache that is external to the apparatus.
1. An apparatus, comprising:
control circuitry;
a non-volatile memory device; and
a volatile memory device, wherein the control circuitry is configured to:
receive a command presented according to a compute express link (CXL) protocol;
determine a type of CXL protocol of the received command;
cause data to be written only to the non-volatile memory device in response to the command being a first type of CXL protocol while refraining from writing the data to a cache that is external to the apparatus:
and cause the data to be written only to the volatile memory device in response to the command being a second type of CXL protocol while refraining from writing the data to the cache that is external to the apparatus.
2. The apparatus of claim 1 , wherein the control circuitry further comprises a universal serial bus interface configured to allow for data to be extracted from the non-volatile memory device or the volatile memory device, or both.
3. The apparatus of claim 1 , wherein the non-volatile memory device and the volatile memory device are resident on a single substrate that is removably couplable to a host system or a motherboard, or both.
4. The apparatus of claim 1 , further comprising a random access memory (RAM) device coupled to the non-volatile memory device and the volatile memory device via a dedicated datapath, wherein the RAM is configured to offload data transfers between the non-volatile memory device and the volatile memory device.
5. The apparatus of claim 1 , wherein the control circuitry comprises a first controller configured to operate according to the CXL protocol, a second controller configured to operate according to a non-volatile memory express protocol, and a third controller configured to operate according to a dual data rate protocol.
6. The apparatus of claim 1 , wherein the control circuitry comprises a first controller configured to exchange CXL.mem commands with the volatile memory device and a second controller configured to exchange CXL.io commands with the non-volatile memory device.
7. The apparatus of claim 1 , wherein the apparatus has a universal storage module form factor.
8. The apparatus of claim 1 , wherein the control circuitry further includes a direct memory access (DMA) component configured to receive the command from a host device.
9. The apparatus of claim 1 , wherein the control circuitry comprises an application-specific integrated circuit.
10. A method, comprising:
receiving a command targeting a memory system that includes a non-volatile memory device and a volatile memory device, wherein the command is presented according to a compute express link (CXL) protocol;
determining a type of CXL protocol of the received command;
causing data to be written only to the non-volatile memory device in response to the command being a first type of CXL protocol while refraining from writing the data to a cache that is external to the non-volatile memory device; and
causing the data to be written only to the volatile memory device, in response to the command being a second type of CXL protocol while refraining from writing the data to the cache that is external to the memory system.
11. The method of claim 10 , further comprising receiving the command targeting the memory system via control circuitry that comprises a memory controller and a storage controller that are resident on the control circuitry.
12. The method of claim 10 , further comprising:
receiving CXL.mem commands by a first portion of control circuitry resident on the memory system; and
receiving CXL.io commands by a second portion of control circuitry resident on the memory system.
13. The method of claim 12 , further comprising:
executing the CXL.mem commands by the first portion of the control circuitry resident on the memory system to access the volatile memory device; and
executing the CXL.io commands by the second portion of the control circuitry resident on the memory system to access the non-volatile memory device.
14. A system, comprising:
a universal storage module (USM) form factor package that includes:
control circuitry;
a non-volatile memory device; and
a volatile memory device, wherein the control circuitry is configured to:
receive a command presented according to a compute express link (CXL) protocol;
determine whether the command is a CXL.mem command or a CXL.io command; and
in response to a determination that the command is a CXL.mem command, cause data to be written only to the volatile memory device while refraining from writing the data to a cache that is external to the USM form factor package, and
in response to a determination that the command is a CXL.io command, cause the data to be written only to the non-volatile memory device while refraining from writing the data to the cache that is external to the USM form factor package.
15. The system of claim 14 , wherein the control circuitry further comprises a universal serial bus interface configured to allow for data to be extracted from the non-volatile memory device or the volatile memory device, or both.
16. The system of claim 14 , further comprising a random access memory (RAM) device coupled to the non-volatile memory device and the volatile memory device via a dedicated datapath, wherein the RAM is configured to offload data transfers between the non-volatile memory device and the volatile memory device.
17. The system of claim 14 , wherein the control circuitry comprises a first controller configured to exchange the CXL.mem command with the volatile memory device and a second controller configured to exchange the CXL.io command with the non-volatile memory device.
18. The system of claim 17 , wherein control circuitry further comprises a third controller configured to operate according to a dual data rate protocol.
19. The system of claim 14 , wherein the control circuitry further includes a direct memory access (DMA) component configured to receive the command from a host device.
20. The system of claim 14 , wherein the control circuitry further comprises a universal serial bus interface configured to allow for data to be extracted from the non-volatile memory device or the volatile memory device, or both.