Gate link across gate cut in semiconductor devices
Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.
1 . An integrated circuit comprising:
a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region;
a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region, the second semiconductor device spaced from the first semiconductor device in a second direction different from the first direction;
a gate electrode around each of the first semiconductor region and the second semiconductor region;
a dielectric wall between the first semiconductor device and the second semiconductor device, such that the gate electrode extends through a portion of the dielectric wall along the second direction, wherein the dielectric wall extends in the first direction between the first source region and the second source region and between the first drain region and the second drain region; and
a dielectric layer on a top surface of the gate electrode, wherein the dielectric layer has a first thickness above the dielectric wall and a second thickness above the first semiconductor device or the second semiconductor device that is at least 1 nm different from the first thickness, the first and second thicknesses being in a third direction different from the first and second directions.
2 . The integrated circuit of claim 1 , wherein the dielectric wall comprises a dielectric layer along one or more edges of the dielectric wall and a dielectric fill in a remaining volume of the dielectric wall.
3 . The integrated circuit of claim 1 , wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons.
4 . The integrated circuit of claim 1 , further comprising a gate dielectric layer around the first semiconductor region and the second semiconductor region, such that the gate dielectric layer is between the first semiconductor region and the gate electrode, and is between the second semiconductor region and the gate electrode.
5 . The integrated circuit of claim 4 , wherein the gate dielectric layer does not extend along any sidewall of the dielectric wall in the third direction.
6 . The integrated circuit of claim 1 , wherein the first thickness of the dielectric layer is greater than the second thickness of the dielectric layer.
7 . The integrated circuit of claim 1 , wherein the dielectric wall is a first dielectric wall and the integrated circuit further comprises:
a second dielectric wall between the first semiconductor device and a third semiconductor device, the second dielectric wall extending through an entire thickness of the gate electrode; and
a third dielectric wall between the second semiconductor device and a fourth semiconductor device, the third dielectric wall extending through an entire thickness of the gate electrode.
8 . An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region;
a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region, the second semiconductor device spaced from the first semiconductor device in a second direction different from the first direction;
a first gate electrode around the first semiconductor region and a second gate electrode around the second semiconductor region;
a gate cut between the first semiconductor device and the second semiconductor device and separating the first and second gate electrodes, the gate cut comprising dielectric material;
a conductive bridge above the gate cut and extending from a sidewall of the first gate electrode to a sidewall of the second gate electrode; and
a dielectric layer on a top surface of the first or second gate electrode and on a top surface of the conductive bridge, wherein the dielectric layer has a first thickness above the conductive bridge and a second thickness above the first or second gate electrode that is at least 2 nm different from the first thickness, the first and second thicknesses being in a third direction different from the first and second directions.
9 . The electronic device of claim 8 , wherein the gate cut comprises a dielectric layer along one or more edges of the gate cut and a dielectric fill in a remaining volume of the gate cut.
10 . The electronic device of claim 8 , further comprising a gate dielectric layer around the first semiconductor region and the second semiconductor region, such that the gate dielectric layer is between the first semiconductor region and the first gate electrode and is between the second semiconductor region and the second gate electrode.
11 . The electronic device of claim 10 , wherein the gate dielectric layer does not extend along any sidewall of the gate cut in the third direction.
12 . The electronic device of claim 8 , wherein the first thickness of the dielectric layer is greater than the second thickness of the dielectric layer.
13 . The electronic device of claim 8 , wherein the gate cut extends in the first direction between the first source region and the second source region and between the first drain region and the second drain region.
14 . An integrated circuit comprising:
a first semiconductor region extending in a first direction between a first source region and a first drain region;
a second semiconductor region extending in the first direction between a second source region and a second drain region, the second semiconductor region spaced from the first semiconductor region in a second direction different from the first direction;
a first gate electrode around the first semiconductor region;
a second gate electrode around the second semiconductor region;
a dielectric wall between the first gate electrode and the second gate electrode; and a conductive bridge extending through a portion of the dielectric wall along the second direction and contacting sidewalls of the first gate electrode and the second gate electrode, wherein the first gate electrode and the second gate electrode have a first width along the first direction and the conductive bridge has a second width along the first direction that is at least 2 nm less than the first width.
15 . The integrated circuit of claim 14 , wherein the dielectric wall comprises a dielectric layer along one or more edges of the dielectric wall and a dielectric fill in a remaining volume of the dielectric wall.
16 . The integrated circuit of claim 15 , wherein the dielectric layer comprises a low-K dielectric material.
17 . The integrated circuit of claim 14 , wherein the conductive bridge comprises a different conductive material than the first gate electrode and the second gate electrode.
18 . The integrated circuit of claim 14 , wherein the conductive bridge comprises molybdenum.