Thin film transistor substrate and display apparatus comprising the same
A thin film transistor substrate and a display apparatus including the same includes a substrate; an active layer and a gate electrode on the substrate, the active layer and gate electrode being spaced apart from each other vertically; a gate insulating film including a first gate insulating film and a second gate insulating film provided between the active layer and the gate electrode; and a source electrode and a drain electrode, each of the source electrode and the drain electrode connected to the active layer. The first gate insulating film is provided closer to the gate electrode than the second gate insulating film, a dielectric constant of the first gate insulating film is higher than a dielectric constant of the second gate insulating film, and a hydrogen content of the first gate insulating film is lower than a hydrogen content of the second gate insulating film.
1 . A thin film transistor substrate, comprising:
a substrate;
an active layer and a gate electrode on the substrate, the active layer and gate electrode being spaced apart from each other vertically;
a gate insulating film including a first gate insulating film and a second gate insulating film provided between the active layer and the gate electrode; and
a source electrode and a drain electrode, each of the source electrode and the drain electrode connected to the active layer,
wherein the first gate insulating film is provided closer to the gate electrode than the second gate insulating film,
wherein a dielectric constant of the first gate insulating film is higher than a dielectric constant of the second gate insulating film,
wherein the first gate insulating film includes silicon nitride formed by plasma-enhanced atomic layer deposition, and the second gate insulating film includes silicon oxide formed by plasma-enhanced atomic layer deposition, and
wherein a hydrogen content of the second gate insulating film at a lower portion of the gate insulating film including the silicon oxide and closer to the active layer is lower than a hydrogen content of the first gate insulating film at an upper portion of gate insulating film including the silicon nitride.
2 . The thin film transistor substrate according to claim 1 , wherein a thickness of the second gate insulating film is in the range of 5% or more and 20% or less than a thickness of the first gate insulating film.
3 . The thin film transistor substrate according to claim 1 , wherein the plasma-enhanced atomic layer deposition is performed using diisopropyl amino silane gas as a source gas.
4 . The thin film transistor substrate according to claim 1 , wherein the silicon oxide is formed by repeatedly performing a first cycle of supplying diisopropylamino silane gas as a first source gas, supplying a first purge gas, supplying a first reactant gas including oxygen with plasma, and supplying a second purge gas into a vacuum chamber, and
wherein the silicon nitride is formed by repeatedly performing a second cycle of supplying diisopropylamino silane gas as a second source gas, supplying a third purge gas, supplying a second reactant gas including nitrogen with plasma, and supplying a fourth purge gas into the vacuum chamber.
5 . The thin film transistor substrate according to claim 1 , wherein the active layer includes an IGZO-based oxide semiconductor formed by a metal organic atomic layer deposition, and a carrier mobility of the active layer is in the range of 22 cm 2 /Vs to 27 cm 2 /Vs.
6 . The thin film transistor substrate according to claim 1 , wherein a dielectric constant of the gate insulating film is in the range of 6.1 to 6.3.
7 . The thin film transistor substrate according to claim 1 , wherein the hydrogen content of the first gate insulating film is 8 atomic % or less.
8 . The Thin film transistor substrate according to claim 1 , wherein the dielectric constant of the first gate insulating film is in the range of 6.0 to 7.5.
9 . A thin film transistor substrate, comprising:
a substrate;
an active layer and a gate electrode on the substrate, the active layer and gate electrode being spaced apart from each other vertically;
a gate insulating film provided between the active layer and the gate electrode; and
a source electrode and a drain electrode, each of the source electrode and the drain electrode connected to the active layer,
wherein the gate insulating film includes silicon nitride and silicon oxide formed by plasma-enhanced atomic layer deposition using diisopropyl amino silane gas as a source gas such that a hydrogen content of a lower portion of the gate insulating film including the silicon oxide and closer to the active layer is lower than a hydrogen content of an upper portion of gate insulating film including the silicon nitride.
10 . The thin film transistor substrate according to claim 9 , wherein the silicon nitride is formed by repeatedly performing one cycle of supplying the diisopropyl amino silane gas as a source gas, supplying a first purge gas, supplying a reactant gas containing nitrogen with plasma, and supplying a second purge gas into a vacuum chamber.
11 . The thin film transistor substrate according to claim 9 , wherein the active layer includes an IGZO-based oxide semiconductor formed by a metal organic atomic layer deposition, and
wherein a carrier mobility of the active layer is in the range of 22 cm 2 /Vs to 27 cm 2 /Vs.
12 . The thin film transistor substrate according to claim 9 , wherein a dielectric constant of the gate insulating film is in the range of 6 to 7.5.
13 . The thin film transistor substrate according to claim 9 , wherein the gate insulating film has a hydrogen content of 8 atomic % or less.
14 . A display apparatus comprising a thin film transistor substrate,
wherein the thin film transistor substrate comprises:
a substrate;
an active layer and a gate electrode on the substrate, the active layer and gate electrode being spaced apart from each other vertically;
a gate insulating film including a first gate insulating film and a second gate insulating film provided between the active layer and the gate electrode; and
a source electrode and a drain electrode, each of the source electrode and the drain electrode connected to the active layer,
wherein the first gate insulating film is provided closer to the gate electrode than the second gate insulating film,
wherein a dielectric constant of the first gate insulating film is higher than a dielectric constant of the second gate insulating film,
wherein the first gate insulating film includes silicon nitride formed by plasma-enhanced atomic layer deposition, and the second gate insulating film includes silicon oxide formed by plasma-enhanced atomic layer deposition, and
wherein a hydrogen content of the second gate insulating film at a lower portion of the gate insulating film including the silicon oxide and closer to the active layer is lower than a hydrogen content of the first gate insulating film at an upper portion of gate insulating film including the silicon nitride.
15 . The display apparatus according to claim 14 , wherein a thickness of the second gate insulating film is in the range of 5% or more and 20% or less than a thickness of the first gate insulating film.
16 . The display apparatus according to claim 14 , wherein the active layer includes an IGZO-based oxide semiconductor formed by a metal organic atomic layer deposition, and a carrier mobility of the active layer is in the range of 22 cm 2 /Vs to 27 cm 2 /Vs.
17 . The display apparatus according to claim 14 , wherein a dielectric constant of the gate insulating film is in the range of 6.1 to 6.3.
18 . The display apparatus according to claim 14 , wherein the hydrogen content of the first gate insulating film is 8 atomic % or less.
19 . The display apparatus according to claim 14 , wherein the dielectric constant of the first gate insulating film is in the range of 6.0 to 7.5.