Recovering scrambling sequence initialization from frozen bits of an uncoded downlink control information vector
A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.
1. A method, comprising:
receiving, by a device, a downlink signal from a base station;
determining, by the device, an input-output relation of polar encoding based on a vector of the downlink signal;
performing, by the device, an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector;
utilizing, by the device, rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal;
utilizing, by the device, a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence; and
decoding, by the device, the downlink signal based on the scrambling sequence initialization vector and without performing a descrambling operation.
2. The method of claim 1 , wherein the downlink signal includes one of:
a physical broadcast channel signal, or
a physical downlink control channel signal.
3. The method of claim 1 , wherein the vector of the downlink signal is an uncoded downlink control information vector.
4. The method of claim 1 , wherein determining the input-output relation of polar encoding based on the vector of the downlink signal comprises:
multiplying the vector and a generator matrix to determine the input-output relation.
5. The method of claim 1 , wherein performing the interleaving operation with the matrix and the input-output relation to obtain the interleaved vector comprises:
multiplying the matrix and the input-output relation to obtain the interleaved vector.
6. The method of claim 1 , wherein utilizing rate matching with the interleaved vector to determine the scrambling sequence of the downlink signal comprises:
determining the scrambling sequence of the downlink signal based on the interleaved vector and a variable that depends on a rate matching scheme.
7. The method of claim 1 , wherein utilizing the reverse sequence generator with the scrambling sequence to determine the scrambling sequence initialization vector for the scrambling sequence comprises:
multiplying the scrambling sequence and a parity check matrix to determine the scrambling sequence initialization vector.
8. The method of claim 1 , wherein the downlink signal includes a signal on a physical channel that carries downlink control information.
9. A device, comprising:
one or more memories; and
one or more processors, coupled to the one or more memories, configured to:
receive a downlink signal from a base station;
determine an input-output relation of polar encoding based on an uncoded downlink control information vector of the downlink signal;
perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector;
utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal;
utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence; and
decode the downlink signal based on the scrambling sequence initialization vector and without performing a descrambling operation.
10. The device of claim 9 , wherein the one or more processors, to utilize the reverse sequence generator with the scrambling sequence to determine the scrambling sequence initialization vector for the scrambling sequence, are configured to:
determine the scrambling sequence initialization vector based on the uncoded downlink control information vector of the downlink signal.
11. The device of claim 9 , wherein the one or more processors, to utilize the reverse sequence generator with the scrambling sequence to determine the scrambling sequence initialization vector for the scrambling sequence, are configured to:
process specific bits of the uncoded downlink control information vector and a parity check matrix, with a belief propagation model, to determine results; and
multiply an inverse matrix and the results to determine the scrambling sequence initialization vector for the scrambling sequence.
12. The device of claim 9 , wherein the downlink signal includes downlink control information.
13. The device of claim 9 , wherein the downlink signal is a New Radio downlink control signal.
14. The device of claim 9 , wherein the downlink signal includes a signal on a physical channel that carries downlink control information.
15. A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:
one or more instructions that, when executed by one or more processors of a device, cause the device to:
receive a downlink signal from a base station,
wherein the downlink signal includes one of:
a physical broadcast channel signal, or
a physical downlink control channel signal;
determine an input-output relation of polar encoding based on a vector of the downlink signal;
perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector;
utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal;
utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence; and
decode the downlink signal based on the scrambling sequence initialization vector and without performing a descrambling operation.
16. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to determine the input-output relation of polar encoding based on the vector of the downlink signal, cause the device to:
multiply the vector and a generator matrix to determine the input-output relation.
17. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to perform the interleaving operation with the matrix and the input-output relation to obtain the interleaved vector, cause the device to:
multiply the matrix and the input-output relation to obtain the interleaved vector.
18. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to utilize rate matching with the interleaved vector to determine the scrambling sequence of the downlink signal, cause the device to:
determine the scrambling sequence of the downlink signal based on the interleaved vector and a variable that depends on a rate matching scheme.
19. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to utilize the reverse sequence generator with the scrambling sequence to determine the scrambling sequence initialization vector for the scrambling sequence, cause the device to:
multiply the scrambling sequence and a parity check matrix to determine the scrambling sequence initialization vector.
20. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to utilize the reverse sequence generator with the scrambling sequence to determine the scrambling sequence initialization vector for the scrambling sequence, cause the device to:
determine the scrambling sequence initialization vector based on the vector of the downlink signal.