Scan driver and display device having the same
A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
1. A scan driver comprising:
a plurality of stages, each of which is configured to control a voltage of a first node in response to a first signal of a previous stage and to output a second signal in response to the voltage of the first node,
wherein an nth stage, where n is a natural number, from among the plurality of stages comprises:
a first transistor coupled between a first terminal configured to receive the first signal and a second node, the first transistor comprising a gate electrode coupled to a second terminal;
a capacitor coupled between the second node and a third terminal;
a second transistor coupled between the third terminal and a third node, the second transistor comprising a gate electrode coupled to the second node; and
a third transistor coupled between the third node and the first node, the third transistor comprising a gate electrode coupled to a fourth terminal.
2. The scan driver of claim 1 , wherein each of the first to third transistors comprises an oxide semiconductor transistor.
3. The scan driver of claim 1 , wherein the first transistor comprises a first sub-transistor and a second sub-transistor, which are coupled in series to each other.
4. The scan driver of claim 1 , wherein the nth stage is configured to store the first signal in the capacitor in response to a third signal supplied to the second terminal, and to transfer a fourth signal supplied to the third terminal to the first node in response to a voltage charged in the capacitor and a fifth signal supplied to the fourth terminal.
5. The scan driver of claim 4 , wherein the fourth signal supplied to the third terminal is a gate-on voltage to turn on an oxide semiconductor transistor.
6. The scan driver of claim 1 , wherein the nth stage is configured to discharge the first node in response to a start signal supplied to a fifth terminal.
7. A display device comprising:
a plurality of pixels respectively coupled to lines; and
a scan driver comprising a plurality of stages configured to supply a second signal to the lines,
wherein each of the stages is configured to control a voltage of a first node in response to a first signal of a previous stage from among the plurality of stages, and to output the second signal in response to the voltage of the first node, and
wherein an nth (n is a natural number) stage from among the plurality of stages comprises:
a first transistor coupled between a first terminal configured to receive the first signal and a second node, the first transistor comprising a gate electrode coupled to a second terminal;
a capacitor coupled between the second node and a third terminal;
a second transistor coupled between the third terminal and a third node, the second transistor comprising a gate electrode coupled to the second node; and
a third transistor coupled between the third node and the first node, the third transistor comprising a gate electrode coupled to a fourth terminal.
8. The display device of claim 7 , wherein the scan driver further comprises a dummy stage configured to provide the first signal to a first stage from among the plurality of stages, and
wherein the dummy stage is electrically separated from the lines.
9. The display device of claim 7 , wherein the first transistor comprises a first sub-transistor and a second sub-transistor, which are coupled in series to each other.