Application specific integrated circuit accelerators
An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.
1. An integrated circuit, comprising:
a systolic array of cells arranged in a plurality of subarrays of cells, wherein:
each cell comprises circuitry for performing an arithmetic computation;
the plurality of subarrays of cells is arranged as a grid extending along a first direction and a second direction;
a plurality of memory circuits, wherein each memory circuit of the plurality of memory circuits is arranged adjacent to a different respective subarray of cells of the plurality of subarrays of cells; and
a vector processing unit, wherein a first subset of the plurality of subarrays of cells is arranged in a first section on a first side of the vector processing unit, and a second subset of the plurality of subarrays of cells is arranged in a second section on a second side of the vector processing unit that is opposite to the first side of the vector processing unit,
the integrated circuit operable to:
transfer a first data set along the first direction to a first subarray of cells of the plurality of subarrays of cells;
transfer a first set of control instructions along the second direction to the first subarray of cells;
perform, by the first subarray of cells and in accordance with the first set of control instructions, the arithmetic computation based on the first data set to obtain a second data set; and
transfer the second data set along the first direction from the first subarray of cells.
2. The integrated circuit of claim 1 , wherein transferring the second data set along the first direction from the first subarray of cells comprises transferring the second data set to a second subarray of cells of the plurality of subarrays of cells.
3. The integrated circuit of claim 1 , wherein the first data set is transferred to the first subarray of cells from a second subarray of cells of the plurality of subarrays of cells.
4. The integrated circuit of claim 3 , wherein the first data set comprises a first partial-sum data set obtained from the second subarray of cells, and wherein the second data set comprises a second partial-sum data set obtained from the first subarray of cells.
5. The integrated circuit of claim 1 , wherein transferring the second data set along the first direction from the first subarray of cells comprises transferring the second data set to a second subarray of cells of the plurality of subarrays of cells, the integrated circuit further operable to:
transfer a second set of control instructions along the second direction to the second subarray of cells;
perform, by the second subarray of cells and in accordance with the second set of control instructions, the arithmetic computation on the second data set to obtain a third data set;
transfer the third data set to the vector processing unit.
6. The integrated circuit of claim 1 , wherein transferring the first data set along the first direction to the first subarray of cells comprises transferring the first data set on at least one controllable bus line.
7. The integrated circuit of claim 6 , wherein the at least one controllable bus line comprises a switch.
8. The integrated circuit of claim 7 , wherein the switch comprises a flip-flop circuit element or a multiplexer.
9. The integrated circuit of claim 6 , wherein transferring the first data set on at least one controllable bus line comprises transferring the first data set according to a predetermined schedule.
10. The integrated circuit of claim 1 , wherein transferring the first set of control instructions along the second direction to the first subarray of cells comprises transferring the first data set on at least one controllable bus line.
11. The integrated circuit of claim 10 , wherein the at least one controllable bus line comprises a switch.
12. The integrated circuit of claim 11 , wherein the switch comprises a flip-flop circuit element or a multiplexer.
13. The integrated circuit of claim 12 , wherein transferring the first set of control instructions on at least one controllable bus line comprises transferring the first set of control instructions according to a predetermined schedule.
14. The integrated circuit of claim 1 , comprising transferring a second data set to the first subarray of cells from a first memory circuit arranged adjacent to the first subarray of cells.
15. The integrated circuit of claim 14 , wherein performing the arithmetic computation is further based on the second data set and on a third data set.
16. The integrated circuit of claim 15 , wherein the first data set comprises a partial-sum data set from a second subarray of cells of the plurality of subarrays of cells, the second data set comprises a plurality of weight inputs, and the third data set comprises a plurality of activation inputs, and wherein the arithmetic computation comprises a multiply and accumulate operation.
17. The integrated circuit of claim 1 , wherein transferring the second data set along the first direction from the first subarray of cells comprises transferring the second data set to a second subarray of cells of the plurality of subarrays of cells, the integrated circuit further operable to:
transfer a second set of control instructions along the second direction to the second subarray of cells;
perform, by the second subarray of cells and in accordance with the second set of control instructions, the arithmetic computation on the second data set to obtain a third data set;
transfer the third data set to the vector processing unit; and
perform a non-linear computation on the third data set in the vector processing unit to provide a vector computation output.
18. The integrated circuit of claim 17 , further comprising transferring the vector computation output to a communication interface coupled to the systolic array of cells.
19. The integrated circuit of claim 1 , comprising storing the first set of control instructions in a first memory circuit arranged adjacent to the first subarray of cells.
20. The integrated circuit of claim 19 , wherein transferring the first set of control instructions along the second direction to the first subarray of cells comprises transferring the first set of control instructions from the first memory circuit to the first subarray of cells.