Regulator with flipped voltage follower architecture
The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.
1. A regulator, comprising:
a bias voltage generating circuit, configured to generate a bias voltage; and
a flipped voltage follower (FVF), configured to generate an output voltage according to the bias voltage and a supply voltage, wherein the FVF comprises:
a first P-type transistor, configured to receive the bias voltage via a gate electrode of the first P-type transistor, to generate the output voltage on a source electrode of the first P-type transistor;
a first N-type transistor, comprising a drain electrode connected to the supply voltage, a source electrode connected to the source electrode of the first P-type transistor, and a gate electrode which receives a first driving signal for compensating the output voltage; and
a second N-type transistor, comprising a drain electrode connected to the supply voltage, a source electrode connected to the source electrode of the first P-type transistor, and a gate electrode which receives a second driving signal for compensating the output voltage.
2. The regulator of claim 1 , wherein the FVF further comprises:
a delay circuit, configured to perform a delay operation on the second driving signal to generate the first driving signal.
3. The regulator of claim 2 , wherein the delay circuit comprises:
a resistor; and
a capacitor, comprising one node connected to the resistor and the gate electrode of the first N-type transistor, and another node connected to a ground voltage.
4. The regulator of claim 1 , wherein the bias voltage generating circuit comprises:
a second P-type transistor, comprising a source electrode for receiving a voltage, a drain electrode coupled to a ground voltage, and a gate electrode configured to generate the bias voltage to the FVF.
5. A regulator, comprising:
a bias voltage generating circuit, configured to generate a bias voltage; and
a flipped voltage follower (FVF), configured to generate an output voltage according to the bias voltage and a supply voltage, wherein the FVF comprises:
a first P-type transistor, configured to receive the bias voltage via a gate electrode of the first P-type transistor, to generate the output voltage on a source electrode of the first P-type transistor;
a first N-type transistor, comprising a drain electrode connected to the supply voltage, a source electrode connected to the source electrode of the first P-type transistor, and a gate electrode which receives a first driving signal for compensating the output voltage;
a third N-type transistor, comprising a drain electrode connected to a drain electrode of the first P-type transistor, and a gate electrode connected to the drain electrode;
a fourth N-type transistor, comprising a gate electrode connected to the gate electrode of the third N-type transistor, wherein the fourth N-type transistor generates the first driving signal on the drain electrode of the fourth N-type transistor; and
a current source, connected to the drain electrode of the fourth N-type transistor.
6. A regulator, comprising:
a bias voltage generating circuit, configured to generate a bias voltage; and
a flipped voltage follower (FVF), configured to generate an output voltage according to the bias voltage and a supply voltage, wherein the FVF comprises:
a first P-type transistor, configured to receive the bias voltage via a gate electrode of the first P-type transistor to generate the output voltage;
a first transistor, connected between the supply voltage and a source electrode of the first P-type transistor, for receiving a first driving signal to compensate the output voltage; and
a second transistor, connected between the supply voltage and the source electrode of the first P-type transistor, for receiving a second driving signal to compensate the output voltage.
7. The regulator of claim 6 , wherein the FVF further comprises:
a delay circuit, configured to perform a delay operation on the second driving signal to generate the first driving signal.
8. The regulator of claim 7 , wherein the delay circuit comprises:
a resistor; and
a capacitor, comprising one node connected to the resistor and a gate electrode of the first transistor, and another node connected to a ground voltage.
9. The regulator of claim 6 , wherein the bias voltage generating circuit comprises:
a second P-type transistor, comprising a source electrode for receiving a voltage, a drain electrode coupled to a ground voltage, and a gate electrode configured to generate the bias voltage to the FVF.