Slope analog-to-digital converter, a system and a method for converting an analog input signal to a digital representation
A slope analog-to-digital converter, ADC, for converting an analog input signal to a digital representation, said slope ADC comprising: a comparator configured to compare two input signals, wherein a sampled value of the analog input signal and a slope signal are used in forming the two input signals; a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog input signal; wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to improve linearity of a transfer function of the slope ADC for converting the analog input signal to the digital representation.
1. A slope analog-to-digital converter, ADC, for converting an analog voltage input signal to a digital representation, said slope ADC comprising:
a comparator configured to compare two input signals, wherein a sampled value of the analog voltage input signal and a slope signal are used in forming the two input signals;
a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog voltage input signal;
wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to compensate for a nonlinearity in processing of the analog voltage input signal.
2. The slope ADC according to claim 1 , further comprising an input unit comprising a sampling capacitor, wherein the input unit is configured to receive the analog voltage input signal and hold the sampled value of the analog voltage input signal on the sampling capacitor, wherein the adaptation of the nonlinear relationship of the slope signal and the counter signal includes a compensation for a nonlinear relation between the analog voltage input signal and the sampled value held by the sampling capacitor.
3. The slope ADC according to claim 1 , wherein the slope signal is configured to vary between a minimum value and a maximum value, wherein the slope signal is monotonically increasing or monotonically decreasing between the minimum value and the maximum value.
4. The slope ADC according to claim 3 , wherein the slope signal is nonlinear in relation to time during monotonical increase or monotonical decrease.
5. The slope ADC according to claim 1 , wherein the counter signal is nonlinear in relation to time.
6. The slope ADC according to claim 1 , wherein said two input signals are the sampled value of the analog voltage input signal and the slope signal such that the comparator is configured to compare the sampled value of the analog voltage input signal and the slope signal.
7. The slope ADC according to claim 1 , wherein the nonlinear relationship between the slope signal and the counter signal is based on a calibration of a nonlinear transfer function of the slope ADC for converting the analog voltage input signal to the digital representation.
8. The slope ADC according to claim 7 , wherein the slope signal is based on a linear monotonically increasing or monotonically decreasing signal in combination with a nonlinear signal based on said calibration.
9. A system for analog-to-digital conversion of analog voltage input signals, wherein the system comprises a plurality of slope ADCs according to claim 1 .
10. The system according to claim 9 , wherein the system comprises a common slope signal generator and a common counter signal generator, such that the plurality of slope ADCs receive the same slope signal and the same counter signal.
11. The system according to claim 10 , wherein the nonlinear relationship between the slope signal and the counter signal is adapted to improve an average error of transfer functions of the plurality of slope ADCs.
12. The system according to claim 9 , wherein the system comprises a time-interleaved arrangement for providing a single analog voltage input signal to the plurality of slope ADCs, wherein the nonlinear relationship of the slope signal and the counter signal is configured to compensate for nonlinearity of the time-interleaved arrangement.
13. The system according to claim 9 , wherein the system is configured to receive a single analog voltage input signal and the plurality of slope ADCs are configured to sample the single analog voltage input signal successively in time for forming a time-interleaved analog-to-digital converter.
14. A method for converting an analog voltage input signal to a digital representation, said method comprising:
comparing by a comparator two input signals, wherein a sampled value of the analog voltage input signal and a slope signal are used in forming the two input signals, wherein a trigger signal is output by the comparator upon identifying a change in which of the two input signals is higher;
receiving by a memory element a counter signal and the trigger signal, and
determining by the memory element a value of the counter signal when the trigger signal is received as the digital representation of the sampled value of the analog voltage input signal, wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to compensate for a nonlinearity in processing of the analog voltage input signal.