IP Library › Granted Patent US 12,182,032
Granted Patent B2
US 12,182,032 · App. 18/136,096 · Granted Dec 31, 2024

Memory migration and page fault avoidance

Inventors: Prashanth Prakash (Santa Clara, CA); Jerome Charles Jean Glisse (Sunnyvale, CA)
Assignee: Google LLC
G06F12/1009G06F12/0822
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Quick Facts
Patent No.
US 12,182,032
App. No.
18/136,096
Granted
Dec 31, 2024
Kind
B2
Abstract

Accessing information associated with a virtual memory address by receiving a virtual memory address, translating the virtual memory address into a nominal physical memory address, receiving the nominal physical memory address at a memory migrator, and using the memory migrator to determine an old physical memory address corresponding to the nominal physical memory address and access the information at the old physical memory address or a new physical memory address. The accessing operation may be performed as part of migrating the information from an old physical memory location corresponding the old physical memory address to a new physical memory location corresponding to the new physical memory address.

Claims (29)

1. A method for accessing information associated with a virtual memory address comprising:

receiving a virtual memory address;

translating the virtual memory address into a nominal physical memory address;

receiving the nominal physical memory address at a memory migrator; and

using the memory migrator to determine an old physical memory address corresponding to the nominal physical memory address and access the information at the old physical memory address,

wherein the steps of receiving a virtual memory address and translating the virtual memory address into a nominal physical memory address are performed within a processor, the memory migrator is located in a coherent-memory device external to the processor, the nominal physical memory address is a fake physical memory address corresponding to the coherent-memory device, and the memory migrator translates the fake physical memory address into the old physical memory address.

2. A system for accessing information associated with a virtual memory address comprising:

one or more processor cores;

at least one memory management unit for receiving a virtual memory address and translating the virtual memory address into a nominal physical memory address; and

a memory migrator for receiving the nominal physical memory address, determining an old physical memory address corresponding to the nominal physical memory address, and accessing the information at the old physical memory address,

wherein the one or more processor cores and the at least one memory management unit are parts of a processor, the memory migrator is located in a coherent-memory device external to the processor, the nominal physical memory address is a fake physical memory address corresponding to the coherent-memory device, and the memory migrator translates the fake physical memory address into the old physical memory address.

3. The system according to claim 2 , wherein the processor further comprises a root complex coupled to the coherent-memory device.

4. A method for performing migration of information associated with a virtual memory address from storage in an old physical memory location corresponding to an old physical memory address to a new physical memory location corresponding to a new physical memory address comprising:

revising a page table cross-referencing the virtual memory address with the old physical memory address to cross-reference the virtual memory address with a nominal physical memory address;

copying the information from the old physical memory location to the new physical memory location; and

when accessing the information using the virtual memory address after revising the page table and before copying the information from the old physical memory location to the new physical memory location:

using the page table to translate the virtual memory address into the nominal physical memory address,

receiving the nominal physical memory address at a memory migrator,

using the memory migrator to determine the old physical memory address based on the nominal physical memory address, and

accessing the information at the old physical memory address; and

when accessing the information using the virtual memory address after revising the page table and after copying the information from the old physical memory location to the new physical memory location:

using the page table to translate the virtual memory address into the new physical memory address or using the memory migrator to determine the new physical memory address based on the nominal physical memory address, and

accessing the information at the new physical memory address.

5. The method according to claim 4 , wherein the memory migrator is located in a processor.

6. The method according to claim 5 , wherein the virtual memory address is generated in the processor.

7. The method according to claim 5 , wherein the virtual memory address is generated by a device external to the processor.

8. The method according to claim 5 , wherein the nominal physical memory address is the new physical memory address, and the new physical memory location is in a memory external to the processor.

9. The method according to claim 4 , wherein the step of using the page table to translate the virtual memory address into the nominal physical memory address is performed within a processor, the memory migrator is located in a coherent-memory device external to the processor, the nominal physical memory address is a fake physical memory address corresponding to the coherent-memory device, and the memory migrator translates the fake physical memory address into the old physical memory address or the new physical memory address.

10. The method according to claim 9 , further comprising the step of revising the page table to replace the fake physical memory address with the new physical memory address.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2023
From: PRAKASH, PRASHANTH; GLISSE, JEROME CHARLES JEAN
To: GOOGLE LLC
Reel/Frame 063493/0766 →
Continuity (1)
Related Publication 20240354257A1 · Oct 24, 2024