Partial block read level voltage compensation to decrease read trigger rates

1. A memory device comprising:

a memory array comprising a plurality of wordlines coupled with respective memory cells of the memory array; and

control logic operatively coupled with the memory array, the control logic to perform operations comprising:

determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed, wherein the determining comprises detecting a pass voltage trip point value associated with a pass voltage applied to wordlines of the one or more strings;

adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and

causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

2. The memory device of claim 1 , wherein the memory cells of the one or more strings have been partially programmed such that at least some of the memory cells are in an erased state.

3. The memory device of claim 1 , wherein the adjusting comprises:

correlating the pass voltage trip point value to a range of a plurality of ranges of the plurality of wordlines that are associated with the memory cells that have been programmed;

retrieving, from a data structure, a voltage offset corresponding to the range; and

adjusting, using the voltage offset, an existing read level voltage.

4. The memory device of claim 1 , wherein the adjusting comprises:

causing a first read calibration to be performed to determine a first voltage offset corresponding to the number of wordlines in a partially-programmed block;

causing a second read calibration to be performed to determine a second voltage offset that compensates for a temporal voltage shift associated with the selected wordline;

combining the first voltage offset and the second voltage offset to determine a total voltage offset; and

adjusting, using the total voltage offset, an existing read level voltage to generate the adjusted read level voltage.

5. The memory device of claim 1 , wherein the determining comprises receiving, from a processing device of a memory sub-system, a percentage value associated with the number of wordlines.

6. The memory device of claim 5 , wherein the percentage value is received in a read command associated with a feature address of the selected wordline.

7. The memory device of claim 5 , wherein the adjusting comprises:

correlating the percentage value to a first voltage offset that compensates for voltage shift corresponding to the number of wordlines in a partial block;

causing a read calibration to be performed to determine a second voltage offset that compensates for a temporal voltage shift associated with selected wordline;

combining the first voltage offset and the second voltage offset to determine a total voltage offset; and

adjusting, using the voltage offset, an existing read level voltage to generate the adjusted read level voltage.

8. A method comprising:

determining, prior to performing a read operation at one or more strings of memory cells of a memory array, a number of wordlines of the one or more strings that are associated with memory cells that have been programmed, wherein the determining comprises detecting a pass volatage trip point value associated with a pass voltage applied to wordlines of the one or more strings;

adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and

causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

9. The method of claim 8 , wherein memory cells of the one or more strings have been partially programmed such that at least some of the memory cells are in an erased state.

10. The method of claim 8 , wherein the adjusting comprises:

correlating the pass voltage trip point value to a range of a plurality of ranges of the number of wordlines of the memory array that are associated with the memory cells that have been programmed;

retrieving, from a data structure, a voltage offset corresponding to the range; and

adjusting, using the voltage offset, an existing read level voltage.

11. The method of claim 8 , wherein the adjusting comprises:

causing a first read calibration to be performed to determine a first voltage offset corresponding to the number of wordlines in a partially-programmed block;

causing a second read calibration to be performed to determine a second voltage offset that compensates for a temporal voltage shift associated with the selected wordline;

combining the first voltage offset and the second voltage offset to determine a total voltage offset; and

adjusting, using the total voltage offset, an existing read level voltage.

12. The method of claim 8 , wherein the determining comprises receiving, from a processing device of a memory sub-system, a percentage value associated with the number of wordlines.

13. The method of claim 12 , wherein the receiving comprises receiving the percentage value in a read command associated with a feature address of the selected wordline.

14. The method of claim 12 , wherein the adjusting comprises:

correlating the percentage value to a first voltage offset that compensates for voltage shift corresponding to the number of wordlines in a partial block;

causing a read calibration to be performed to determine a second voltage offset that compensates for a temporal voltage shift associated with selected wordline;

combining the first voltage offset and the second voltage offset to determine a total voltage offset; and

adjusting, using the voltage offset, an existing read level voltage to generate the adjusted read level voltage.

15. A memory sub-system comprising:

a memory device comprising a memory array comprising a plurality of wordlines coupled with respective memory cells of the memory array; and

a processing device coupled with the memory device, the processing device to perform operations comprising:

identifying a number of wordlines of a block of memory cells of the memory array that are associated with memory cells that have been programmed;

determining a voltage offset corresponding to the number of wordlines;

determining a read level voltage using the voltage offset; and

sending a read command to the memory device that includes the read level voltage and an address of a selected wordline of the memory array that is to be read.

16. The memory sub-system of claim 15 , wherein the determining the voltage offset comprises:

accessing a data structure in which ranges of the plurality of wordlines that have been programmed are indexed against different voltage offsets; and

indexing, using a value representing the number of wordlines, within the data structure to determine the voltage offset.

17. The memory sub-system of claim 15 , wherein determining the read level voltage comprises:

causing a first calibration to be performed to determine a first voltage offset corresponding to the number of wordlines in a partially-programmed block;

causing a second read calibration to be performed to determine a second voltage offset that compensates for a temporal voltage shift associated with the selected wordline;

combining the first voltage offset and the second voltage offset to determine a total voltage offset; and

adjusting, using the total voltage offset, an existing read level voltage to be applied to the selected wordline.

18. The memory sub-system of claim 15 , wherein the operations further comprise generating the read command to include the read level voltage that incorporates the voltage offset.