Granted Patent B1

US 12,210,427 · App. 18/139,148 · Granted Jan 28, 2025

Inventors: Jason Hamlet (Albuquerque, NM); Tom Mannos (Albuquerque, NM)

Assignee: National Technology & Engineering Solutions of Sandia, LLC

G06F11/184G06F11/261G06F30/327

Abstract

Claims (75)

1. A method for circuit modification for fault mitigation, the method comprising:

obtaining a netlist defining a circuit;

inserting at least one saboteur circuit into a first net of the netlist;

configuring an FPGA to implement the first net and the at least one saboteur circuit;

activating a first of the at least one saboteur circuits;

determining whether the first net experiences a fault;

upon determining that the first net experiences a fault, modifying the first net by inserting at least one redundant circuit into the first net;

obtaining a modified netlist corresponding to the netlist and the at least one redundant circuit;

inserting a second saboteur circuit into a first net of the modified netlist;

configuring the FPGA to implement the first net of the modified netlist and the second saboteur circuit;

activating the second saboteur circuit;

testing the first net of the modified netlist;

determining whether the first net of the modified netlist passes the testing;

upon determining that the first net of the modified netlist passes the testing, retaining the at least one redundant circuit in the modified netlist; and

upon determining that the first net of the modified netlist does not pass the testing, removing the at least one redundant circuit from the modified netlist.

2. The method of claim 1 wherein modifying the first net by inserting at least one redundant circuit into the first net comprises:

identifying original logic in the first net;

inserting at least two redundant logic elements in parallel with the original logic; and

providing an output of the original logic and outputs of the at least two redundant logic elements to a majority voter.

3. The method of claim 2 wherein the at least two redundant logic elements includes at least one diverse implementation of the original logic.

4. The method of claim 2 wherein a total number of outputs from the original logic and the at least two redundant logic elements is an odd number.

5. The method of claim 1 wherein determining whether the first net experiences a fault comprises determining whether the first net experiences a severe fault.

6. The method of claim 1 further comprising:

determining that the first net includes an untested, second of the at least one saboteur circuits;

activating the second of the at least one saboteur circuits;

determining whether the first net experiences a second fault; and

upon determining that the first net experiences a second fault, modifying the first net by inserting at least one second redundant circuit into the first net.

7. The method of claim 1 further comprising:

determining that the netlist includes a second net without a saboteur circuit;

inserting a second saboteur circuit into the second net;

configuring the FPGA to implement the second net and the second saboteur circuit;

activating the second saboteur circuit;

determining whether the second net experiences a fault; and

upon determining that the second net experiences a fault, modifying the second net by inserting at least one second redundant circuit into the second net.

8. A system that is configured for circuit modification for fault mitigation, the system comprising:

a processor; and

a memory that stores instructions that, when executed by the processor, causes the processor to perform acts comprising:

obtaining a netlist defining a circuit;

inserting a saboteur circuit into a first net of the netlist;

configuring an FPGA to implement the first net and the saboteur circuit;

activating the saboteur circuit;

determining whether the first net experiences a fault;

upon determining that the first net experiences a fault, modifying the first net by inserting at least one redundant circuit into the first net;

obtaining a modified netlist corresponding to the netlist and the at least one redundant circuit;

inserting a second saboteur circuit into a first net of the modified netlist;

configuring the FPGA to implement the first net of the modified netlist and the second saboteur circuit;

activating the second saboteur circuit;

testing the first net of the modified netlist;

determining whether the first net of the modified netlist passes the testing;

upon determining that the first net of the modified netlist passes the testing, retaining the at least one redundant circuit in the modified netlist; and

upon determining that the first net of the modified netlist does not pass the testing, removing the at least one redundant circuit from the modified netlist.

9. A computer program comprising a computer-readable non-transitory storage medium, the computer program including instructions for causing a processor to implement a process of circuit modification for fault mitigation, the process comprising:

obtaining a netlist defining a circuit;

inserting a saboteur circuit into a first net of the netlist;

configuring an FPGA to implement the first net and the saboteur circuit;

activating the saboteur circuit;

determining whether the first net experiences a fault;

upon determining that the first net experiences a fault, modifying the first net by inserting at least one redundant circuit into the first net;

obtaining a modified netlist corresponding to the netlist and the at least one redundant circuit;

inserting a second saboteur circuit into a first net of the modified netlist;

configuring the FPGA to implement the first net of the modified netlist and the second saboteur circuit;

activating the second saboteur circuit;

testing the first net of the modified netlist;

determining whether the first net of the modified netlist passes the testing;

upon determining that the first net of the modified netlist passes the testing, retaining the at least one redundant circuit in the modified netlist; and

upon determining that the first net of the modified netlist does not pass the testing, removing the at least one redundant circuit from the modified netlist.

10. A method for circuit validation, the method comprising:

obtaining a modified netlist corresponding to a netlist and at least one modification;

inserting a saboteur circuit into a first net of the modified netlist;

configuring an FPGA to implement the first net of the modified netlist and the saboteur circuit;

activating the saboteur circuit;

testing the first net of the modified netlist;

determining whether the first net of the modified netlist passes the testing;

upon determining that the first net of the modified netlist passes the testing, retaining the at least one modification in the modified netlist; and

upon determining that the first net of the modified netlist does not pass the testing, removing the at least one modification from the modified netlist.

Assignments (2)

References Cited (16)