IP Library › Granted Patent US 12,730,591
Granted Patent B2
US 12,730,591 · App. 18/139,198 · Granted Sep 8, 2026

Systems and methods for storage based monitoring of memory accesses

Inventors: Mukesh Garg (Stanford, CA); Ramzi Ammari (Santa Clara, CA); Changho Choi (San Jose, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F3/0671G06F3/061G06F3/0653
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Quick Facts
Patent No.
US 12,730,591
App. No.
18/139,198
Granted
Sep 8, 2026
Kind
B2
Abstract

Systems and methods for monitoring memory accesses. A storage system comprises a first memory device, a second memory device, and a controller configured to communicate with the first memory device and the second memory device. The controller is configured to: receive, from a computing device, a first request for first data; identify a first address based on the first request; search the first memory device for the first address; modify a first count maintained in the second memory device for the first address; receive from the computing device a second request; and provide the first count in response to the second request.

Claims (43)

1 . A storage system comprising:

a first memory device;

a second memory device; and

a controller configured to communicate with the first memory device and the second memory device, the controller being configured to:

receive, from a computing device, a first request for first data, the first request including a first process identifier associated with a first process, wherein the first request is generated according to a compute express link memory (CXL.mem) protocol;

identify a first address based on the first request;

search the first memory device for the first address;

modify a first count in the second memory device for the first address, wherein the first count is stored in association with the first process identifier;

receive from the computing device a second request, wherein the second request is generated according to the CXL.mem protocol, the second request includes information of the first address and the first process identifier; and

provide the first count based on the information of the first address and the first process identifier.

2 . The storage system of claim 1 , wherein the first memory device is associated with a first access latency.

3 . The storage system of claim 1 , wherein the first memory device is coupled to the computing device over a communication interface.

4 . The storage system of claim 1 , wherein the first request includes at least one of a request to load or store the first data.

5 . The storage system of claim 1 , wherein the first count is indicative of a number of accesses to the first address.

6 . The storage system of claim 1 , wherein the second memory device is configured to maintain a third count for a second address in the first memory device.

7 . The storage system of claim 6 , wherein the controller is configured to provide the third count in response to the second request.

8 . The storage system of claim 7 , wherein the computing device is configured to:

compare the first count to the third count; and

cause an action in response to the compare.

9 . The storage system of claim 8 , wherein the first count is greater than the third count, and the computing device is configured to maintain second data, associated with the second address, in the first memory device based on the compare.

10 . The storage system of claim 1 , wherein the controller is further configured to:

receive from the computing device a third request from the computing device; and

update the first count in response to the third request.

11 . A method comprising:

receiving, from a process running on a computing device, a first request for first data, the first request including a first process identifier associated with a first process, wherein the first request is generated according to a compute express link memory (CXL.mem) protocol;

identifying a first address based on the first request;

searching a first memory device for the first address;

modifying a first count in a second memory device for the first address, wherein the first count is stored in association with the first process identifier;

receiving from the computing device a second request, wherein the second request is generated according to the CXL.mem protocol, the second request includes information of the first address and the first process identifier; and

providing the first count based on the information of the first address and the first process identifier.

12 . The method of claim 11 , wherein the first memory device is associated with a first access latency.

13 . The method of claim 11 , wherein the first memory device is coupled to the computing device over a communication interface.

14 . The method of claim 11 , wherein the first request includes at least one of a request to load or store the first data.

15 . The method of claim 11 , wherein the first count is indicative of a number of accesses to the first address.

16 . The method of claim 11 further comprising:

maintaining, by the second memory device, a third count for a second address in the first memory device.

17 . The method of claim 16 further comprising:

providing the third count in response to the second request.

18 . The method of claim 17 further comprising:

comparing, by the computing device, the first count to the third count; and

causing an action in response to the comparing.

19 . The method of claim 18 , wherein the first count is greater than the third count, the method further comprising:

maintaining second data, associated with the second address, in the first memory device based on the comparing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2023
From: GARG, MUKESH; AMMARI, RAMZI; CHOI, CHANGHO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 063792/0642 →
Continuity (2)
Provisional Application 63451601 · Mar 12, 2023
Related Publication 20240303001A1 · Sep 12, 2024
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