IP Library Granted Patent US 12,176,039
Granted Patent B2
US 12,176,039 · App. 18/140,103 · Granted Dec 24, 2024

Setting levels for a programming operation in a neural network array

Inventors: Hieu Van Tran (San Jose, CA); Stanley Hong (San Jose, CA); Stephen Trinh (San Jose, CA); Thuan Vu (San Jose, CA); Steven Lemke (Boulder Creek, CA); Vipin Tiwari (Dublin, CA); Nhan Do (Saratoga, CA)
Assignee: SILICON STORAGE TECHNOLOGY, INC.
G11C16/10G06N3/065G11C11/5628G11C16/0425G11C16/0433G11C16/14G11C16/3459
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Quick Facts
Patent No.
US 12,176,039
App. No.
18/140,103
Granted
Dec 24, 2024
Kind
B2
Abstract

In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.

Claims (18)

1. A method comprising:

determining a program resolution current value; and

setting N current levels for a plurality of non-volatile memory cells in a neural network array, where the non-volatile memory cells respectively can be programmed to any of the N current levels, such that a delta current between adjacent current levels within the N current levels is a multiple of the program resolution current value;

wherein the delta current is at least a 1 sigma variation of one of the N current levels.

2. The method of claim 1 , wherein at least one of the N current levels is a multiple of an off cell leakage value.

3. The method of claim 1 , wherein the plurality of non-volatile memory cells are organized into logical cells, each logical cell comprising one or more coarse cells and one or more fine cells.

4. The method of claim 3 , wherein the non-volatile memory cells are split gate flash memory cells.

5. The method of claim 3 , wherein the non-volatile memory cells are stacked gate flash memory cells.

6. The method of claim 1 , wherein the non-volatile memory cells are split gate flash memory cells.

7. The method of claim 1 , wherein the non-volatile memory cells are stacked gate flash memory cells.

8. A method comprising:

determining a program resolution current value; and

setting N current levels for a plurality of non-volatile memory cells in a neural network array, where the non-volatile memory cells respectively can be programmed to any of the N current levels, such that a delta current between adjacent current levels within the N current levels is a multiple of the program resolution current value;

wherein the delta current is at least a 2 sigma variation of one of the N current levels.

9. A method comprising:

determining a program resolution current value; and

setting N current levels for a plurality of non-volatile memory cells in a neural network array, where the non-volatile memory cells respectively can be programmed to any of the N current levels, such that a delta current between adjacent current levels within the N current levels is a multiple of the program resolution current value;

wherein the delta current is at least a 3 sigma variation of one of the N current levels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2025
From: TRAN, HIEU VAN; HONG, STANLEY; TRINH, STEPHEN; VU, THUAN; LEMKE, STEVEN; TIWARI, VIPIN; DO, NHAN
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 070603/0280 →
Continuity (3)
Division 17082956 · Oct 28, 2020
Provisional Application 63024351 · May 13, 2020
Related Publication 20230268004A1 · Aug 24, 2023