Emulation of JTAG/SCAN test interface protocols using SPI communication device

1. An apparatus for joint test action group (JTAG) and scan emulation, the apparatus comprising:

a controller circuitry that is interfaced to a target integrated circuit (IC) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices operating in master mode and slave mode, the one or more SPI devices having a plurality of pins to perform JTAG and scan emulation, the plurality of pins configured to:

emulate JTAG testing by using a clock (CLK) pin of a master SPI device to serve as a test clock (TCK) signal to a slave SPI device and the target IC;

provide a master output slave input (MOSI) pin of the master SPI device as a test data input (TDI) signal to the target IC;

provide a master input slave output (MISO) pin of the slave SPI device as a test mode select (TMS) signal for the target IC;

receive, from the target IC, a test data output (TDO) signal by the master input slave output (MISO) pin of the master SPI device; and

emulate scan testing by using the CLK pin of the master SPI device to serve as a serial clock (SCK) signal to the slave SPI device and the target IC;

provide the MOSI pin of the master SPI device and MISO pin of the slave SPI device as serial data input (SDI) signals to the target IC; and

receive, from the target IC, serial data output (SDO) signals by the MISO pin of the master SPI device and the MOSI pin of the slave SPI device, wherein the controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.

2. The apparatus as claimed in claim 1 , wherein the controller circuitry operates the one or more SPI devices to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality, wherein extended multiple scan chain is possible with dual/quad SPI devices or multiple SPI devices.

3. The apparatus as claimed in claim 1 , wherein the controller circuitry operates the one or more SPI devices to emulate the JTAG testing in a first mode, in which the one or more SPI devices comprise a first SPI device that operates in the master mode and a second SPI device operate in the slave mode.

4. The apparatus as claimed in claim 3 , wherein the controller circuitry is configured to:

connect a master chip select signal to slave chip select signal;

generate, by the first SPI device operating in the master mode, the TCK signal for communication;

load the TDI data in the first SPI device operating in the master mode;

load the TMS data in the second SPI device operating in the slave mode, wherein the data are transmitted in TDI and TMS lines; and

store the TDO data received from the target IC in a shift register of the first SPI device operating in the master mode.

5. The apparatus as claimed in claim 3 , wherein the controller circuitry operates the one or more SPI devices to emulate the JTAG testing in the second mode, in which both the first SPI device and the second SPI device operate in the slave mode, wherein the controller circuitry is configured to:

load the TMS data into the second SPI device operating in the slave mode;

load the TDI data into the first SPI device operating in the slave mode;

enable slave select (NSS) pin of the first SPI device and the second SPI device operating in the slave mode, the NSS pin connected to a general-purpose input/output (GPIO) pin;

enable an Universal Asynchronous Receiver Transmitter (UART) circuit to transmit the TCK signal for the first SPI device and the second SPI device operating in the slave mode; and

store the TDO data received from the target IC in a shift register of the first SPI device operating in the slave mode.

6. The apparatus as claimed in claim 3 , wherein the controller circuitry operates the one or more SPI devices to emulate a single scan chain testing in the first mode, in which at least one SPI device operates in the master mode, the controller circuitry is configured to:

load the SDI data into the first SPI device operating in the master mode;

generate, by the first SPI device operating in master mode, the SCK signal for communication;

control scan reset by a GPIO pin;

enable a NSS pin of the first SPI device operating in the master mode; and

store the SDO data received from the target IC in a shift register of the first SPI device operating in the master mode.

7. The apparatus as claimed in claim 3 , wherein the controller circuitry operates the one or more SPI devices to emulate a single scan chain testing in the second mode, at least one SPI device operates in the slave mode, wherein the controller circuitry is configured to:

load the SDI data into the first SPI device operating in the slave mode;

control scan reset and scan enable (SEN) by a GPIO pin;

enable a NSS pin of the first SPI device operating in the slave mode by the GPIO pin;

enable a UART circuit to transmit the SCK signal for the first SPI device operating in the slave mode; and

store the SDO data received from the target IC in a shift register of the first SPI device operating in the slave mode.

8. The apparatus as claimed in claim 3 , wherein the controller circuitry operates the one or more SPI devices to emulate a dual scan chain testing in the first mode, in which the first SPI device operating in the master mode and the second SPI device operating in the slave mode, wherein the dual scan chain testing includes at least two SDI signals and at least two SDO signals to speed the testing of the target IC.

9. The apparatus as claimed in claim 3 , wherein the controller circuitry operates the one or more SPI devices to emulate a dual scan chain testing in the first mode, the controller circuitry is configured to:

connect master chip select signal to slave chip select signal which is on a NSS pin of the second SPI device operating in the slave mode;

generate the SCK signal by the first SPI device operating in the master mode for communication;

load SDI0 data in the first SPI device operating in the master mode;

load SDI1 data in the second SPI device operating in the slave mode;

control scan reset and scan enable (SEN) by a GPIO pin;

enable the NSS pin of the second SPI device operating in the slave mode; and

store SDO0 data and SDO1 data received from the target IC in a shift register of the first SPI device operating in the master mode and the second SPI device operating in the slave mode.

10. The apparatus as claimed in claim 3 , wherein the controller circuitry operates the one or more SPI devices to emulate dual scan chain testing in the second mode, in which both the first SPI device and the second SPI device operate in the slave mode, wherein the controller circuitry configured to:

load SDI0 into the first SPI device operating in the slave mode;

load SDI1 into the second SPI device operating in the slave mode;

control scan reset and scan enable (SEN) by a GPIO pin;

enable a NSS pin of the first SPI device and the second SPI device operating in the slave mode by the GPIO pin;

enable a UART circuit to transmit the SCK signal for the first SPI device and the second SPI device operating in the slave mode; and

store SDO0 data and SDO1 data received from the target IC in a shift register of the first SPI device and the second SPI device operating in the slave mode.