SiC substrate and SiC epitaxial wafer
In a SiC substrate of the present invention, in a case where the SiC substrate is supported on an inner periphery by an inner peripheral support surface positioned to overlap a circumference having a radius of 17.5 mm from a center, in a case where a plane connecting first points of an upper surface overlapping the inner peripheral support surface when seen in a thickness direction is defined as a first reference plane, and an upper side of the first reference plane is defined as a positive side, a bow is less than 40 μm.
1. A SiC substrate,
wherein, in a case where the SiC substrate is supported on an inner periphery by an inner peripheral support surface positioned to overlap a circumference having a radius of 17.5 mm from a center, the SiC substrate deflects upward,
in a case where a plane connecting first points of an upper surface overlapping the inner peripheral support surface when seen in a thickness direction is defined as a first reference plane, and an upper side of the first reference plane is defined as a positive side, a bow is less than 40 μm and
a diameter is 145 mm or more.
2. The SiC substrate according to claim 1 ,
wherein a warp in a case where the SiC substrate is supported by the inner peripheral support surface is less than 60 μm.
3. The SiC substrate according to claim 1 ,
wherein, in a case where the SiC substrate is supported on an outer periphery by an outer peripheral support surface positioned to overlap a circumference 7.5 mm inside from an outermost periphery,
in a case where a plane connecting second points of the upper surface overlapping the outer peripheral support surface when seen in the thickness direction is defined as a second reference plane, and an upper side of the second reference plane is defined as a positive side, a bow is more than −40 μm.
4. The SiC substrate according to claim 3 ,
wherein, in a case where the SiC substrate is supported on the outer periphery by the outer peripheral support surface, a bow with respect to the second reference plane is 0 μm or less.
5. The SiC substrate according to claim 3 ,
wherein a warp in a case where the SiC substrate is supported by the outer peripheral support surface is less than 60 μm.
6. The SiC substrate according to claim 1 ,
wherein a diameter is 195145 mm or more.
7. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 1 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
8. The SiC substrate according to claim 1 ,
wherein the bow in a case where the SiC substrate is supported by the inner peripheral support surface is less than 10 μm.
9. The SiC substrate according to claim 1 ,
wherein a warp in a case where the SiC substrate is supported by the inner peripheral support surface is less than 20 μm.
10. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 2 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
11. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 3 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
12. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 4 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
13. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 5 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
14. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 6 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
15. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 8 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.
16. A SiC epitaxial wafer comprising:
the SiC substrate according to claim 9 ; and
a SiC epitaxial layer stacked on one surface of the SiC substrate.