Data processing engine arrangement in a device

1. A device, comprising:

a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns;

wherein each data processing engine includes a core, a memory module including a memory, and a direct memory access engine;

wherein each data processing engine includes a stream switch, wherein the stream switch of each data processing engine is connected to the core and the direct memory access engine in a same data processing engine, and to the stream switch of one or more adjacent data processing engines;

wherein each memory module includes a plurality of memory interfaces including a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines; and

wherein each core coupled to a selected memory interface of the plurality of memory interfaces of a selected memory module is configured to access the memory of the selected memory module via the selected memory interface independently of the stream switch.

2. The device of claim 1 , wherein a memory module of a first data processing engine is configured to receive data streamed via the stream switch and the direct memory access engine included therein from at least one of a non-adjacent data processing engine or an adjacent data processing engine.

3. The device of claim 1 , wherein a memory module of a first data processing engine is configured to receive data streamed via the stream switch and the direct memory access engine included therein from a non-adjacent data processing engine; and

wherein a core of the first data processing engine is configured to directly access data from the memory module included therein and directly access data from a memory module of an adjacent data processing engine.

4. The device of claim 1 , wherein each data processing engine comprises:

a hardware synchronization circuit including a plurality of hardware locks configured to control access to the memory module in the same data processing engine; and

wherein the hardware synchronization circuit arbitrates access to the memory module between cores of the one or more adjacent data processing engines with direct access and one or more non-adjacent data processing engines coupled via the stream switch and the direct memory access engine.

5. The device of claim 1 , further comprising:

a processor coupled to the data processing engine array, wherein the processor is configured to control operation of the data processing engine array.

6. The device of claim 5 , wherein the processor is configured to reconfigure at least a portion of the data processing engine array in response to a detected condition in the device.

7. The device of claim 5 , wherein the processor, in response to a detected condition in the device, is configured to load new data into one or more selected memory modules of the data processing engine array.

8. The device of claim 5 , wherein the processor is configured to control application parameters stored in the memory module of one or more of the plurality of data processing engines in response to a detected condition in the device.

9. The device of claim 5 , wherein one or more of the plurality of data processing engines is operative as a kernel that uses parameters stored in a selected memory module at runtime; and

wherein the processor, in response to a detected condition in the device, is configured to calculate new parameters dynamically at runtime of the data processing engine array and store the new parameters in the selected memory module.

10. A device, comprising:

a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns;

wherein each data processing engine includes a core, a memory module including a memory, and a direct memory access engine;

wherein each data processing engine includes a stream switch, wherein the stream switch of each data processing engine is connected to the core and the direct memory access engine in a same data processing engine, and the stream switch of one or more adjacent data processing engines;

wherein each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines;

wherein each data processing engine further comprises a hardware synchronization circuit including a plurality of hardware locks configured to control access to the memory module in the same data processing engine; and

wherein the hardware synchronization circuit is configured to arbitrate access to the memory module between cores of the one or more adjacent data processing engines with direct access and one or more non-adjacent data processing engines coupled via the stream switch and the direct memory access engine.

11. The device of claim 10 , wherein a memory module of a first data processing engine is configured to receive data streamed via the stream switch and the direct memory access engine included therein from a non-adjacent data processing engine.

12. The device of claim 10 , wherein a second data processing engine is configured to directly access data from the memory module included therein and directly access data from a memory module of an adjacent data processing engine.

13. The device of claim 10 , wherein a memory module of a first data processing engine is configured to receive data streamed via the stream switch and the direct memory access engine included therein from a non-adjacent data processing engine; and

wherein a core of the first data processing engine is configured to directly access data from the memory module included therein and directly access data from a memory module of an adjacent data processing engine.

14. The device of claim 10 , further comprising:

a processor coupled to the data processing engine array, wherein the processor is configured to control operation of the data processing engine array.

15. The device of claim 14 , wherein the processor is configured to reconfigure at least a portion of the data processing engine array in response to a detected condition in the device.

16. The device of claim 14 , wherein the processor, in response to a detected condition in the device, is configured to load new data into one or more selected memory modules of the data processing engine array.

17. The device of claim 14 , wherein the processor is configured to control application parameters stored in the memory module of one or more of the plurality of data processing engines in response to a detected condition in the device.

18. The device of claim 14 , wherein one or more of the plurality of data processing engines is operative as a kernel that uses parameters stored in a selected memory module at runtime; and

wherein the processor, in response to a detected condition in the device, is configured to calculate new parameters dynamically at runtime of the data processing engine array and store the new parameters in the selected memory module.

19. The device of claim 1 , wherein, within each memory module, the direct memory access engine, the first memory interface, and the one or more second memory interfaces are coupled to a plurality of arbiter circuits within the memory module, the plurality of arbiter circuits configured to arbitrate among memory accesses received over a plurality of different data paths corresponding to the direct memory access engine, the first memory interface and the one or more second memory interfaces.