Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher
Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
1. A method comprising:
receiving, from a host computing device, a write command, an address, and write data for a memory device;
responsive to the write command:
generating an error correction code for the write data;
generating an access code by using the address as an initialization vector for an authenticated stream cipher; and
concurrent to generation of the access code, performing address translation using the write command and the address to translate a logical memory address of the address to a physical memory address of the memory device; and
performing a write operation associated with the write command using the access code, the write data, the error correction code, and the physical memory address.
2. The method of claim 1 , further comprising receiving the write command, the address, and the write data from the host device at a cache of a memory controller via a host bus.
3. The method of claim 1 , wherein the authenticated stream cipher comprises an advanced encryption standard (AES) cipher.
4. The method of claim 3 , further comprising generating, at a Galois/Counter Mode (GCM) of an authentication logic circuit, the access code based on the AES cipher.
5. The method of claim 1 , further comprising encrypting the write data and the error correction code using the access code.
6. The method of claim 5 , further comprising performing an XOR-operation with the access code and the write data and the error correction code to generate ciphertext during encryption of the write data and the error correction code.
7. The method of claim 6 , further comprising generating an authentication tag to be associated with the ciphertext for writing of the ciphertext to the physical address based partly on a result of the XOR-operation of the access code and the write data and the error correction code.
8. The method of claim 7 , further comprising writing, at the physical address of the memory device, the ciphertext as part of the write operation.
9. The method of claim 1 , further comprising generating the error correction code based on a parity-check correction code.
10. The method of claim 1 , further comprising generating the error correction code based on single error correction, double error detection error correction code algorithm.
11. An apparatus comprising:
authentication logic circuitry configured to receive a write come and, write data, and an address, wherein the authentication logic circuitry is further configured to generate an access code by using the address as an initialization vector for a stream cipher; and
translation logic circuitry configured to, concurrent with generation of the access code, perform address translation using the write command and the address to translate a logical memory address of the address to a physical memory address;
a cache configured to store the write data; and
a memory device configured to perform a write operation associated with the write command using the access code, the write data, and the physical memory address.
12. The apparatus of claim 11 , further comprising an error correction unit circuit configured to generate an error correction code associated with the write data, wherein the write operation further includes the error correction code.
13. The apparatus of claim 11 , wherein the error correction unit circuit comprises a low-density parity-check correction algorithm unit, configured to generate the error correction code.
14. The apparatus of claim 11 , wherein the error correction unit circuit comprises a single error correction, double error detection algorithm error correction code unit circuit configured to generate the error correction code.
15. The apparatus of claim 11 , wherein the memory device includes a NAND memory device.
16. The apparatus of claim 11 , wherein memory controller is configured to receive the write command, the write data, and the address from a host computing device via a PCIe bus.
17. The apparatus of claim 11 , wherein the authentication logic circuitry s configured to execute a Galois/Counter Mode (GCM) to generate the access code with the stream cipher as the authenticated stream cipher.
18. The apparatus of claim 17 , wherein the authenticated stream cipher comprises an advanced encryption standard (AES)-GCM pipeline.
19. The apparatus of claim 17 , wherein authentication logic circuitry is further configured to use the access code to encrypt the write data as ciphertext.
20. The apparatus of claim 11 , further the translation logic circuitry is further configured to translate the write data provided to the memory device.