Prefetch store filtering

1. A data processing apparatus comprising:

prefetch circuitry configured to generate a prefetch request for a cache line prior to the cache line being explicitly requested, wherein the cache line is predicted to be required for a store operation in the future;

issuing circuitry to issue the prefetch request to a memory hierarchy; and

filter circuitry configured to filter out the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry,

wherein the filter circuitry is configured to filter out the prefetch request based on an amount of the cache line that is required by the at least one other prefetch request made to the cache line.

2. The data processing apparatus according to claim 1 , wherein

the filter circuitry is configured to filter out the prefetch request such that the prefetch request is inhibited from being issued by the issue circuitry in response to all of the cache line being predicted as being accessed by one or more predicted accessed for which the at least one other prefetch request is generated.

3. The data processing apparatus according to claim 1 , wherein

the filter circuitry is configured to filter out the prefetch request such that the prefetch request is issued by the issue circuitry in response to only a part of the cache line being predicted as being accessed by one or more predicted accesses for which the at least one other prefetch request is generated.

4. The data processing apparatus according to claim 1 , wherein

the at least one other prefetch request is one of a predetermined number of recent prefetch requests.

5. The data processing apparatus according to claim 1 , comprising:

a store buffer configured to buffer store operations prior to being issued to the memory hierarchy, wherein the store buffer is configured to merge those of the store operations that are directed towards a same cache line.

6. The data processing apparatus according to claim 5 , wherein

the filter circuitry is configured to store a plurality of entries, each of the entries having an associated cache line; and

for each of the entries, the filter circuitry is configured to track parts of the associated cache line to which the at least one other prefetch request has been made.

7. The data processing apparatus according to claim 6 , wherein

a capacity of the store buffer is at least as big as a capacity of the filter circuitry.

8. The data processing apparatus according to claim 6 , wherein

the filter circuitry is configured to store, for each of the entries, an N-bit bitfield to indicate which of the N bytes of the associated cache line are predicted as being accessed by predicted accesses for which the at least one other prefetch request—is generated.

9. The data processing apparatus according to claim 6 , wherein

the filter circuitry is configured to store, for each of the entries, an offset within the associated cache line; and

an indication of which of:

bytes in the cache line above the offset and

bytes in the are predicted as being accessed by predicted accesses for which the at least one other prefetch request is generated.

10. The data processing apparatus according to claim 9 , wherein

the offset is represented using a log 2 (N) bit bitfield, where N is the number of fragments of the associated cache line that are individually tracked; and

the indication is represented using a 1-bit field.

11. The data processing apparatus according to claim 1 , wherein

the prefetch request is a store prefetch request; and

the at least one other prefetch request is at least one other store prefetch request.

12. A data processing method comprising:

generating a prefetch request for a cache line prior to the cache line being explicitly requested, wherein the cache line is predicted to be required for a store operation in the future;

filtering the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued; and

issuing the prefetch request to a memory hierarchy in dependence on the filtering,

wherein the prefetch request is filtered out based on an amount of the cache line that is required by the at least one other prefetch request made to the cache line.

13. A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus comprising:

prefetch circuitry configured to generate a prefetch request for a cache line prior to the cache line being explicitly requested, wherein the cache line is predicted to be required for a store operation in the future;

issuing circuitry to issue the prefetch request to a memory hierarchy; and

filter circuitry configured to filter out the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry,

wherein the filter circuitry is configured to filter out the prefetch request based on an amount of the cache line that is required by the at least one other prefetch request made to the cache line.