Data transmission method, timing controller, and storage medium

1. A data transmission method, applicable to a timing controller, the method comprising:

sending clock calibration data to a source driver chip, wherein the dock calibration data instructs the source driver chip to perform dock calibration;

sending, in response to completing the clock calibration by the source driver chip, first configuration information to the source driver chip over a data channel, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and

after the source driver chip has performed the configuration on the physical layer parameter based on the first configuration information, sending a link stable pattern and then sending display data to the source driver chip.

2. The method according to claim 1 , wherein the first configuration information comprises at least one of drive current configuration information, equalizer gain configuration information, and dock data recovery loop bandwidth configuration information of the source driver chip.

3. The method according to claim 1 , after successively sending the link stable pattern and the display data to the source driver chip, further comprising:

re-sending, in response to a lock loss of the source driver chip, the dock calibration data to the source driver chip; and

sending, in response to completing the clock calibration by the source driver chip, second configuration information to the source driver chip over the data channel, wherein the second configuration information instructs the source driver chip to re-perform the configuration on the physical layer parameter.

4. The method according to claim 1 , wherein the display data comprises any row of pixel data in a frame of data, the row of pixel data corresponding to a row control instruction; and

wherein the row control instruction comprises first power indication information, the first power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a horizontal blank period.

5. The method according to claim 2 , wherein the display data comprises any row of pixel data in a frame of data, the row of pixel data corresponding to a row control instruction; and

wherein the row control instruction comprises first power indication information, the first power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a horizontal blank period.

6. The method according to claim 3 , wherein the display data comprises any row of pixel data in a frame of data, the row of pixel data corresponding to a row control instruction; and

wherein the row control instruction comprises first power indication information, the first power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a horizontal blank period.

7. The method according to claim 1 , wherein the display data comprises a last row of pixel data in a frame of data, the last row of pixel data corresponding to a frame control instruction; and

wherein the frame control instruction comprises second power indication information, the second power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a vertical blank period.

8. The method according to claim 2 , wherein the display data comprises a last row of pixel data in a frame of data, the last row of pixel data corresponding to a frame control instruction; and

wherein the frame control instruction comprises second power indication information, the second power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a vertical blank period.

9. The method according to claim 3 , wherein the display data comprises a last row of pixel data in a frame of data, the last row of pixel data corresponding to a frame control instruction; and

wherein the frame control instruction comprises second power indication information, the second power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a vertical blank period.

10. The method according to claim 1 , wherein there are a plurality of data channels;

wherein sending the first configuration information to the source driver chip over the data channel comprises;

sending the first configuration information to the source driver chip over each of the plurality of data channels, wherein the first configuration information sent over each data channel instructs the source driver chip to perform the configuration on the physical layer parameter corresponding to the data channel.

11. The method according to claim 10 , wherein the first configuration information is different over at least two of the plurality of data channels.

12. A timing controller, comprising a processor, a transceiver, and a memory;

wherein the memory stores one or more instructions executable by the processor; and

the processor, when loading and running the one or more instructions, is caused to control the transceiver to perform:

sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration;

sending, in response to completing the clock calibration by the source driver chip, first configuration information to the source driver chip over a data channel, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and

after the source driver chip has performed the configuration on the physical layer parameter based on the first configuration information, sending a link stable pattern and then sending display data to the source driver chip.

13. The timing controller according to claim 12 , wherein the first configuration information comprises at least one of drive current configuration information, equalizer gain configuration information, and clock data recovery loop bandwidth configuration information of the source driver chip.

14. The timing controller according to claim 12 , wherein the processor, when loading and running the one or more instructions, is caused to control the transceiver to perform:

re-sending, in response to a lock loss of the source driver chip, the clock calibration data to the source driver chip; and

sending, in response to completing the clock calibration by the source driver chip, second configuration information to the source driver chip over the data channel, wherein the second configuration information instructs the source driver chip to re-perform the configuration on the physical layer parameter.

15. The timing controller according to claim 12 , wherein the display data comprises any row of pixel data in a frame of data, the row of pixel data corresponding to a row control instruction; and

wherein the row control instruction comprises first power indication information, the first power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a horizontal blank period.

16. The timing controller according to claim 12 , wherein the display data comprises a last row of pixel data in a frame of data, the last row of pixel data corresponding to a frame control instruction; and

wherein the frame control instruction comprises second power indication information, the second power indication information indicating whether the timing controller and the source driver chip enter a low-power mode in a vertical blank period.

17. The timing controller according to claim 12 , wherein there are a plurality of data channels;

wherein the processor, when loading and running the one or more instructions, is caused to control the transceiver to perform:

sending the first configuration information to the source driver chip over each of the plurality of data channels, wherein the first configuration information sent over each data channel instructs the source driver chip to perform the configuration on the physical layer parameter corresponding to the data channel.

18. The timing controller according to claim 17 , wherein the first configuration information is different over at least two of the plurality of data channels.

19. A non-transitory computer-readable storage medium, storing one or more computer programs, wherein the one or more computer programs, when loaded and executed by a computer, cause the computer to perform:

sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration;

sending, in response to completing the clock calibration by the source driver chip, first configuration information to the source driver chip over a data channel, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and

after the source driver chip has performed the configuration on the physical layer parameter based on the first configuration information, sending a link stable pattern and then sending display data to the source driver chip.

20. The non-transitory computer-readable storage medium according to claim 19 , wherein the first configuration information comprises at least one of drive current configuration information, equalizer gain configuration information, and clock data recovery loop bandwidth configuration information of the source driver chip.