Dies, semiconductor package structures, enable pin configuration methods and memories
In one example, a peripheral circuit in a die is configured to: first, receive control commands, and generate indication information according to the control commands, the control commands being used for indicating the die to determine the address of the die, the indication information being used for indicating M dies to share the same enable pin, M being a positive integer greater than or equal to 1; and then, determine the address of the die according to the indication information, and send the address of the die, the address being used for addressing an enable signal provided by the enable pin.
1. A die comprising a peripheral circuit, the peripheral circuit configured to:
receive control commands, the control commands for indicating the die to determine an address of the die;
generate indication information for M dies based on the control commands, the indication information to include address encoding information of the M dies, the indication information being used for indicating the M dies to share a same enable pin, M being a positive integer greater than or equal to 1;
determine the address of a die of the M dies based on the indication information, wherein to determine the address further includes to decode the indication information to produce a first encoded value based on a number of dies sharing the same enable pin and to decode the first encoded value to obtain the address of the die; and
send the address of the die to a main control chip, the main control chip to enable the die via an enable signal provided by the same enable pin to the address.
2. The die of claim 1 , wherein the peripheral circuit includes:
a control circuit, a trigger, a first decoding circuit, and a second decoding circuit, which are coupled in sequence;
the control circuit is configured to receive the control commands, generate the indication information based on the control commands, and send the indication information;
the trigger is configured to receive the indication information and send the indication information to the first decoding circuit;
the first decoding circuit is configured to determine the first encoded value of the die based on the indication information; and
the second decoding circuit is configured to decode the first encoded value to obtain the address of the die.
3. The die of claim 2 , wherein the peripheral circuit further includes a register coupled with the first decoding circuit, and the first decoding circuit is further configured to set a first numerical value in the register to be a second numerical value, the first numerical value is used for indicating that an encoded value of the die is a second encoded value, and the second numerical value is used for indicating that the encoded value of the die is the first encoded value.
4. The die of claim 3 , wherein values of M include 1, 2, 4, 8, 16 or 32.
5. A semiconductor package structure, wherein the semiconductor package structure comprises N dies configured to at least:
receive control commands using M dies among the N dies, the control commands for indicating a die to determine an address of the die, and wherein M is a positive integer greater than or equal to 1, N is a positive integer greater than or equal to 2, and M is less than or equal to N;
generate indication information for M dies based on the control commands, the indication information to include address encoding information of the M dies, the indication information being used for indicating the M dies to share a same enable pin;
determine the address of the die of the M dies based on the indication information, wherein to determine the address further includes to decode the indication information to produce a first encoded value based on a number of dies sharing the same enable pin and to decode the first encoded value to obtain the address of the die; and
send the address of the die to a main control chip via the M dies, the main control chip to enable the die via an enable signal provided by the same enable pin to the address.
6. The semiconductor package structure of claim 5 , wherein when M is greater than or equal to 2, encoded values of the M dies are different from each other.
7. The semiconductor package structure of claim 6 , wherein the M dies include a target die therein, wherein the target die is used for receiving chip selection signals, the chip selection signals are used for selecting the target die to receive the enable signal and include the address of the target die.
8. An enable pin configuration method of a die, wherein the die includes a peripheral circuit, and the method comprises:
receiving, by the peripheral circuit, control commands, the control commands for indicating the die to determine an address of the die;
generating indication information for M dies based on the control commands, the indication information including address encoding information of the M dies, the indication information being used for indicating the M dies to share a same enable pin, M being a positive integer greater than or equal to 1;
determining, by the peripheral circuit, the address of the die based on the indication information, wherein determining the address further includes to decode the indication information to produce a first encoded value based on a number of dies sharing the same enable pin and to decode the first encoded value to obtain the address of the die; and
sending the address of the die to a main control chip, the main control chip to enable the die via an enable signal provided by the same enable pin to the address.
9. The method of claim 8 , wherein the peripheral circuit includes a control circuit, a trigger, a first decoding circuit, and a second decoding circuit, which are coupled in sequence, and the method further includes:
receiving, by the control circuit, the control commands, generating the indication information based on the control commands, and sending the indication information;
receiving, by the trigger, the indication information, and sending the indication information to the first decoding circuit;
determining, by the first decoding circuit, the first encoded value of the die based on the indication information; and
decoding, by the second decoding circuit, the first encoded value to obtain the address of the die.
10. The method of claim 9 , wherein the peripheral circuit further includes a register coupled with the first decoding circuit, and the method further includes setting, by the first decoding circuit, a first numerical value in the register to be a second numerical value, the first numerical value being used for indicating that an encoded value of the die is a second encoded value, the second numerical value being used for indicating that the encoded value of the die is the first encoded value.
11. The method of claim 10 , wherein values of M include 1, 2, 4, 8, 16 or 32.